Bo-Qiao Lin

According to our database, Bo-Qiao Lin authored at least 4 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.

Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Graph-Based Logic Bit Slicing for Datapath-Aware Placement.

Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages.

Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.

Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015