Bo Liu

Orcid: 0000-0001-6776-1988

Affiliations:
  • Henan University of Science and Technology, Electrical Engineering College, Luoyang, China
  • University of Kitakyushu, Fukuoka, Japan


According to our database1, Bo Liu authored at least 30 papers between 2010 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2025
EDRP-GTDQN: An adaptive routing protocol for energy and delay optimization in wireless sensor networks using game theory and deep reinforcement learning.
Ad Hoc Networks, 2025

2024
A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology.
J. Circuits Syst. Comput., May, 2024

Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator.
Microelectron. J., January, 2024

Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL.
Microelectron. J., 2024

Erratum: A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology.
J. Circuits Syst. Comput., 2024

FDIA localization and classification detection in smart grids using multi-modal data and deep learning technique.
Comput. Electr. Eng., 2024

2023
BP Neural Network Modeling and Solving Acceleration of Analog ICs.
Circuits Syst. Signal Process., December, 2023

Discrimination strategy using machine learning technique for oestrus detection in dairy cows by a dual-channel-based acoustic tag.
Comput. Electron. Agric., July, 2023

High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICs.
Circuits Syst. Signal Process., April, 2023

A multi-objective parameter optimization approach to maximize lifetime of wireless sensor networks inspired by spider web.
J. Supercomput., 2023

Adaptive particle swarm optimization based hybrid small-signal modeling of GaN HEMT.
Microelectron. J., 2023

2022
IACRA: Lifetime Optimization by Invulnerability-Aware Clustering Routing Algorithm Using Game-Theoretic Approach for Wsns.
Sensors, 2022

Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm.
Microelectron. J., 2022

A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout.
Integr., 2022

Large-Signal Behavior Modeling of GaN P-HEMT Based on GA-ELM Neural Network.
Circuits Syst. Signal Process., 2022

2021
An improved GaN P-HEMT small-signal equivalent circuit with its parameter extraction.
Microelectron. J., 2021

2019
Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO.
J. Circuits Syst. Comput., 2019

Density Optimization for Analog Layout Based on Transistor-Array.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2018
Routable and Matched Layout Styles for Analog Module Generation.
ACM Trans. Design Autom. Electr. Syst., 2018

2017
Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration.
Proceedings of the New Generation of CAS, 2017

Explicit layout pattern density controlling based on transistor-array-style.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
A <i>Ku</i>-Band Low-Phase-Noise Cross-Coupled VCO in GaAs HBT Technology.
J. Circuits Syst. Comput., 2016

A multi-functional memory unit with PLA-based reconfigurable decoder.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Routability of twisted common-centroid capacitor array under signal coupling constraints.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Twin-row-style for MOS analog layout.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2012
Layout-Aware Variability Characterization of CMOS Current Sources.
IEICE Trans. Electron., 2012

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
D-A converter based variation analysis for analog layout design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010


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