Bo Liu

Affiliations:

Beijing Institute of Control Engineering, On-Board Computer and Electronic Technology Laboratory, Beijing, China
Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (PhD 2005)

According to our database¹, Bo Liu authored at least 11 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

2023

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Cross-Layer Optimization for Fault-Tolerant Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2023

2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Flip-flop clustering based trace signal selection for post-silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Path constraint solving based test generation for observability-enhanced branch coverage.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2013

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Off-path leakage power aware routing for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Bo Liu

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...