Bo Hu

Affiliations:
  • Flexlogics Inc., Santa Clara, CA, USA
  • University of California, Santa Barbara, CA, USA (PhD 2004)


According to our database1, Bo Hu authored at least 15 papers between 2001 and 2007.

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Timeline

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Bibliography

2007
mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2005
Multilevel fixed-point-addition-based VLSI placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

mFAR: fixed-points-addition-based VLSI placement algorithm.
Proceedings of the 2005 International Symposium on Physical Design, 2005

2004
Individual wire-length prediction with application to timing-driven placement.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Fine granularity clustering-based placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Fast postplacement optimization using functional symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Multilevel expansion-based VLSI placement with blockages.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Wire length prediction in constraint driven placement.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Fine granularity clustering for large scale placement problems.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Synthesis and placement flow for gain-based programmable regular fabrics.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Gain-based technology mapping for discrete-size cell libraries.
Proceedings of the 40th Design Automation Conference, 2003

Wire length prediction based clustering and its application in placement.
Proceedings of the 40th Design Automation Conference, 2003

2002
FAR: fixed-points addition & relaxation based placement.
Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion minimization during placement without estimation.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
In-place delay constrained power optimization using functional symmetries.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001


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