Bo-Chuan Cheng

According to our database¹, Bo-Chuan Cheng authored at least 7 papers between 2011 and 2017.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2017

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

2016

An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

2014

Optimized Pre-bond Test Methodology for Silicon Interposer Testing.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

De Bruijn graph-based communication modeling for fault tolerance in smart grids.

[BibT_eX]

[DOI]

Bo-Chuan Cheng

Katherine Shu-Min Li

Sying-Jyan Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A Unified Interconnects Testing Scheme for 3D Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Bo-Chuan Cheng

Timeline

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