Bo-Cheng Lai
Orcid: 0000-0002-9729-5196Affiliations:
- University of California, Los Angeles, USA
According to our database1,
Bo-Cheng Lai
authored at least 77 papers
between 2002 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on ee.ucla.edu
On csauthors.net:
Bibliography
2024
Down-Sampling Inter-Layer Adapter for Parameter and Computation Efficient Ultra-Fine-Grained Image Recognition.
CoRR, 2024
Global-Local Similarity for Efficient Fine-Grained Image Recognition with Vision Transformers.
CoRR, 2024
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
IEEE ACM Trans. Comput. Biol. Bioinform., 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023
2022
Frontiers Big Data, 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
DAF: re: A Challenging, Crowd-Sourced, Large-Scale, Long-Tailed Dataset For Anime Character Recognition.
CoRR, 2021
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Novel Smart Assistance System for Blood Vessel Approaching: A Technical Report Based on Oximetry.
Sensors, 2020
J. Parallel Distributed Comput., 2020
Dataflow and microarchitecture co-optimisation for sparse CNN on distributed processing element accelerator.
IET Circuits Devices Syst., 2020
IEEE Comput. Archit. Lett., 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
2018
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning.
J. Parallel Distributed Comput., 2018
Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
IEEE Trans. Computers, 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the 10th International Conference on Complex, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2015
IEEE Trans. Computers, 2015
J. Parallel Distributed Comput., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 18th International Conference on Network-Based Information Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
2014
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2014
ACM Trans. Design Autom. Electr. Syst., 2014
Proceedings of the Network and Parallel Computing, 2014
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the International Conference on Parallel and Distributed Computing, 2013
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Reduce Data Coherence Cost with an Area Efficient Double Layer Counting Bloom Filter.
Proceedings of the Fifth International Symposium on Parallel Architectures, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012
2011
Classifier Grouping to Enhance Data Locality for a Multi-threaded Object Detection Algorithm.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011
2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2008
IEEE Trans. Computers, 2008
2006
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.
IEEE J. Solid State Circuits, 2006
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005
Proceedings of the Ambient Intelligence, 2005
2004
Reducing radio energy consumption of key management protocols for wireless sensor networks.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks: Third International Conference, 2004
2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
A Security Protocol for Biometric Smart Cards.
Proceedings of the Fifth Smart Card Research and Advanced Application Conference, 2002