Björn Franke
Orcid: 0000-0002-1219-8523Affiliations:
- University of Edinburgh
According to our database1,
Björn Franke
authored at least 76 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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on dl.acm.org
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Bibliography
2024
J. Syst. Softw., 2024
Proceedings of the 25th ACM SIGPLAN/SIGBED International Conference on Languages, 2024
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024
Proceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction, 2024
2022
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2022
2021
Proceedings of the PPoPP '21: 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
Parallelizing Parallel Programs: A Dynamic Pattern Analysis for Modernization of Legacy Parallel Code.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Proceedings of the 28th International Conference on Compiler Construction, 2019
2018
Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.
Proc. IEEE, 2018
Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018
Proceedings of the 27th International Conference on Compiler Construction, 2018
Proceedings of the 27th International Conference on Compiler Construction, 2018
2017
Free Rider: A Source-Level Transformation Tool for Retargeting Platform-Specific Intrinsic Functions.
ACM Trans. Embed. Comput. Syst., 2017
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Efficient asynchronous interrupt handling in a full-system instruction set simulator.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016
Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
2015
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2015
Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Experiences in speeding up computer vision applications on mobile computing platforms.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015
2014
ACM Trans. Archit. Code Optim., 2014
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Measuring QoE of interactive workloads and characterising frequency governors on mobile devices.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
Proceedings of the Compiler Construction - 23rd International Conference, 2014
Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators.
Proceedings of the 2014 International Conference on Compilers, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Int. J. Parallel Program., 2013
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011
Selecting the optimal system: automated design of application-specific systems-on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
2010
Workload characterization supporting the development of domain-specific compiler optimizations using decision trees for data mining.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010
Empirical evaluation of data transformations for network infrastructure applications.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.
Proceedings of the CGO 2010, 2010
Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
ACM Trans. Embed. Comput. Syst., 2009
Towards a holistic approach to auto-parallelization: integrating profile-driven parallelism detection and machine-learning based mapping.
Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009
Proceedings of the Languages and Compilers for Parallel Computing, 2009
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, 2008
Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, 2008
Proceedings of the 22nd British HCI Group Annual Conference on HCI 2008: People and Computers XXII: Culture, Creativity, Interaction, 2008
2007
A Cost-Aware Parallel Workload Allocation Approach Based on Machine Learning Techniques.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007
Fast compiler optimisation evaluation using code-feature based performance prediction.
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006
2005
IEEE Trans. Parallel Distributed Syst., 2005
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005
2004
Compilation techniques for high-performance embedded systems with multiple processors.
PhD thesis, 2004
2003
ACM Trans. Embed. Comput. Syst., 2003
Informationsquelle Mitarbeiter.
Proceedings of the Innovationen im E-Business, 2003
Compiler parallelization of C programs for multi-core DSPs with multiple address spaces.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
2001
Proceedings of the Compiler Construction, 10th International Conference, 2001
Proceedings of the 2001 International Conference on Compilers, 2001