Bishnu Prasad Das
Orcid: 0000-0001-6993-2744
According to our database1,
Bishnu Prasad Das
authored at least 38 papers
between 2006 and 2024.
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Bibliography
2024
Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
2022
In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2019
An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications.
Microelectron. J., 2019
A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Metastability immune and area efficient error masking flip-flop for timing error resilient designs.
Integr., 2018
2017
Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2014
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
J. Intell. Manuf., 2013
2012
A framework for collaboration moderator services to support knowledge based collaboration.
J. Intell. Manuf., 2012
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation.
IET Circuits Devices Syst., 2012
Application of Collaboration Moderator Service in Pharmaceutical Industry: A Collaborative Drug Discovery Use Case.
Proceedings of the Enterprise Interoperability V, 2012
2010
Proceedings of the Collaborative Networks for a Sustainable World, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2008
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
A review of approaches to supply chain communications: from manufacturing to construction.
J. Inf. Technol. Constr., 2007
Towards the understanding of the requirements of a communication language to support process interoperation in cross-disciplinary supply chains.
Int. J. Comput. Integr. Manuf., 2007
2006
Data Sci. J., 2006