Binsu J. Kailath
Orcid: 0000-0003-1249-4063
According to our database1,
Binsu J. Kailath
authored at least 18 papers
between 2016 and 2025.
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Bibliography
2025
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025
2024
Development of Accurate Model for Memristor-Based Filters and Oscillators: Amplitude, Frequency and Ramp-Rate Dependent Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2022
2021
Int. J. Circuit Theory Appl., 2021
Tree/link method for transfer function and stability analysis of switched-capacitor circuits.
Int. J. Circuit Theory Appl., 2021
Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons.
Proceedings of the IEEE World AI IoT Congress, 2021
Proceedings of the IEEE World AI IoT Congress, 2021
2020
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020
Proceedings of the 2020 IEEE Symposium Series on Computational Intelligence, 2020
2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
2018
IET Circuits Devices Syst., 2018
2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur.
IEICE Electron. Express, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016