Binod Kumar
Orcid: 0000-0002-0479-9855Affiliations:
- Indian Institute of Technology Jodhpur, India
According to our database1,
Binod Kumar
authored at least 35 papers
between 2016 and 2023.
Collaborative distances:
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on dl.acm.org
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Bibliography
2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test.
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs.
ACM J. Emerg. Technol. Comput. Syst., 2020
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
2019
J. Circuits Syst. Comput., 2019
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.
J. Electron. Test., 2019
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
2017
A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors.
J. Low Power Electron., 2017
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Revisiting random access scan for effective enhancement of post-silicon observability.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
RTL level trace signal selection and coverage estimation during post-silicon validation.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016