Bingwei Jiang

According to our database, Bingwei Jiang authored at least 6 papers between 2016 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Maximum Efficiency Tracking for Dynamic WPT System Based on Optimal Input Voltage Matching.

Hao He, Songcen Wang, Youwei Liu, Cheng Jiang, Xiaokang Wu, Bin Wei, Bingwei Jiang

IEEE Access, 2020

2019

A 23-mW 60-GHz Differential Sub-Sampling PLL with an NMOS-Only Differential-Inductively-Tuned VCO.

Bingwei Jiang, Howard C. Luong

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector.

Zhiqiang Huang, Bingwei Jiang, Howard C. Luong

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A 7.9-GHz Transformer-Feedback Quadrature Oscillator With a Noise-Shifting Coupling Network.

Bingwei Jiang, Howard C. Luong

IEEE J. Solid State Circuits, 2017

2016

2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL.

Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network.

Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016