Bing Li

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

Machine Learning in Advanced IC Design: A Methodological Survey.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

Early Classification for Dynamic Inference of Neural Networks.

[BibT_eX]

[DOI]

Jingcun Wang

CoRR, 2023

Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2023

Area-Efficient Neural Network CD Equalizer for 4×200Gb/s PAM4 CWDM4 Systems.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

NearUni: Near-Unitary Training for Efficient Optical Neural Networks.

[BibT_eX]

[DOI]

Amro Eldebiky

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Class-based Quantization for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test.

[BibT_eX]

[DOI]

Amro Eldebiky

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Mixer-Based Washing Methods for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., October, 2022

VirtualSync+: Timing Optimization With Virtual Synchronization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Contamination-Aware Synthesis for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2022

Aging Aware Retraining for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

An Efficient Programming Framework for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Bayesian Inference Based Robust Computing on Memristor Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Test Generation for Flow-Based Microfluidic Biochips With General Architectures.

[BibT_eX]

[DOI]

Bhargab B. Bhattacharya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).

[BibT_eX]

[DOI]

CoRR, 2020

Countering Variations and Thermal Effects for Accurate Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Reliable and Robust RRAM-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.

[BibT_eX]

[DOI]

Gautam Choudhary

Sandeep Pal

Debraj Kundu

Sukanta Bhattacharjee

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Timing Resilience for Efficient and Secure Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Fault Localization in Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

Alessandro Bernardini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Tsun-Ming Tseng

Mengchu Li

Daniel Nestor Freitas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

Alessandro Bernardini

Microelectron. J., 2018

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.

[BibT_eX]

[DOI]

Masanori Hashimoto

IPSJ Trans. Syst. LSI Des. Methodol., 2018

Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.

[BibT_eX]

[DOI]

Bhargab B. Bhattacharya

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Automatic Design of Microfluidic Devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Forum on Specification & Design Languages, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Design-for-testability for continuous-flow microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2017

Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers.

[BibT_eX]

[DOI]

CoRR, 2017

Application of machine learning methods in post-silicon yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Design automation for Labs-on-Chip: A new "playground" for SoC designers.

[BibT_eX]

[DOI]

Robert Wille

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

W3B: Special session: Secure multi-processors systems-on-chip for critical applications.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Testing microfluidic Fully Programmable Valve Arrays (FPVAs).

[BibT_eX]

[DOI]

Bhargab B. Bhattacharya

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

From biochips to quantum circuits: computer-aided design for emerging technologies.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Control-fluidic CoDesign for paper-based digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Sampling-based buffer insertion for post-silicon yield improvement under process variability.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Columba: co-layout synthesis for continuous-flow microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Timing verification for adaptive integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2013

On Timing Model Extraction and Hierarchical Statistical Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Post-route alleviation of dense meander segments in high-performance printed circuit boards.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Post-route refinement for high-frequency PCBs considering meander segment alleviation.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Iterative timing analysis based on nonlinear and interdependent flipflop modelling.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2012

Variation-aware leakage power model extraction for system-level hierarchical power analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Iterative Timing Analysis Considering Interdependency of Setup and Hold Times.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Timing Modeling of Flipflops Considering Aging Effects.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Sensitivity based parameter reduction for statistical analysis of circuit performance.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Timing model extraction for sequential circuits considering process variations.

[BibT_eX]

[DOI]