Bing Li
Orcid: 0000-0001-9752-7201Affiliations:
- Technical University of Munich, Institute for Electronic Design Automation, Germany
According to our database1,
Bing Li
authored at least 122 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
CoRR, 2024
CoRR, 2024
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks.
CoRR, 2024
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration.
CoRR, 2024
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, February, 2023
IEEE Des. Test, February, 2023
Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks.
CoRR, 2023
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., October, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization.
IEEE Trans. Computers, 2022
ACM Comput. Surv., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters.
ACM Trans. Design Autom. Electr. Syst., 2019
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices.
Microelectron. J., 2018
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol., 2018
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers.
CoRR, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
W3B: Special session: Secure multi-processors systems-on-chip for critical applications.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
Proceedings of the 54th Annual Design Automation Conference, 2017
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling.
Proceedings of the 54th Annual Design Automation Conference, 2017
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Sampling-based buffer insertion for post-silicon yield improvement under process variability.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Des. Test, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping.
Proceedings of the 52nd Annual Design Automation Conference, 2015
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Post-route alleviation of dense meander segments in high-performance printed circuit boards.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Post-route refinement for high-frequency PCBs considering meander segment alleviation.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IET Circuits Devices Syst., 2012
Variation-aware leakage power model extraction for system-level hierarchical power analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Sensitivity based parameter reduction for statistical analysis of circuit performance.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008