Bing-Chuan Bai

According to our database, Bing-Chuan Bai authored at least 6 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.

Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li

Proceedings of the 22nd Asian Test Symposium, 2013

2009

Power scan: DFT for power switches in VLSI designs.

Bing-Chuan Bai, Chien-Mo James Li, Augusli Kifli, Even Tsai, Kun-Cheng Wu

Proceedings of the 2009 IEEE International Test Conference, 2009

Fault modeling and testing of retention flip-flops in low power designs.

Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC.

Yu-Te Liaw, Bing-Chuan Bai, James Chien-Mo Li

J. Inf. Sci. Eng., 2008

2007

Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique.

Bo-Hua Chen, Wei-Chung Kao, Bing-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li

Proceedings of the 16th Asian Test Symposium, 2007