Bindu G. Gowda
Orcid: 0000-0003-2797-2363
According to our database1,
Bindu G. Gowda
authored at least 12 papers
between 2022 and 2024.
Collaborative distances:
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Bibliography
2024
OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022