Bin Li

Affiliations:
  • Intel Labs, Hillsboro, OR, USA
  • Princeton University, NJ, USA (PhD 2009)


According to our database1, Bin Li authored at least 22 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
RAPID: Enabling fast online policy learning in dynamic public cloud environments.
Neurocomputing, November, 2023

PROMPT: Learning dynamic resource allocation policies for network applications.
Future Gener. Comput. Syst., August, 2023

2022
PROMPT: Learning Dynamic Resource Allocation Policies for Edge-Network Applications.
CoRR, 2022

DPM-NFV: Dynamic Power Management Framework for 5G User Plane Function using Bayesian Optimization.
Proceedings of the IEEE Global Communications Conference, 2022

2021
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization.
IEEE Comput. Archit. Lett., 2021

MOBO-NFV: Automated Tuning of a Network Function Virtualization System using Multi-Objective Bayesian Optimization.
Proceedings of the 17th IFIP/IEEE International Symposium on Integrated Network Management, 2021

2020
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization.
Proceedings of the 6th IEEE Conference on Network Softwarization, 2020

2018
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

2014
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A systematic network-on-chip traffic modeling and generation methodology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
EMERALD: Characterization of emerging applications and algorithms for low-power devices.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012
ORION 2.0: A Power-Area Simulator for Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Dynamic QoS management for chip multiprocessors.
ACM Trans. Archit. Code Optim., 2012

Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs.
J. Parallel Distributed Comput., 2011

Cost-effectively offering private buffers in SoCs and CMPs.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Template-based memory access engine for accelerators in SoCs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact.
IEEE Comput. Archit. Lett., 2010

2009
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006


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