Biman Chattopadhyay

According to our database, Biman Chattopadhyay authored at least 9 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process.

Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016

A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS.

Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2013

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS.

Anant S. Kamath, Biman Chattopadhyay

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process.

Ravi Mehta, Sumantra Seth, Siddharth Shashidharan, Biman Chattopadhyay, Sujoy Chakravarty

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

A 1.8GHz Digital PLL in 65nm CMOS.

Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS.

Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth.

Anant S. Kamath, Biman Chattopadhyay

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0.

Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009