Bill Lin
Orcid: 0000-0003-0965-7247Affiliations:
- University of California at San Diego, Department of Electrical and Computer Engineering, La Jolla, USA
According to our database1,
Bill Lin
authored at least 191 papers
between 1987 and 2024.
Collaborative distances:
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Timeline
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Online presence:
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on linkedin.com
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on orcid.org
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on cwc.ucsd.edu
On csauthors.net:
Bibliography
2024
A Practical Recipe for Federated Learning Under Statistical Heterogeneity Experimental Design.
IEEE Trans. Artif. Intell., April, 2024
Rethinking Data Heterogeneity in Federated Learning: Introducing a New Notion and Standard Benchmarks.
IEEE Trans. Artif. Intell., March, 2024
Towards Diverse Device Heterogeneous Federated Learning via Task Arithmetic Knowledge Integration.
CoRR, 2024
CoRR, 2024
CoRR, 2024
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations.
CoRR, 2024
Monolithic Silicon-Photonics Linear-Algebra Accelerators Enabling Next-Gen Massive MIMO.
CoRR, 2024
2023
IEEE Trans. Artif. Intell., October, 2023
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst., July, 2023
Mach. Learn. Knowl. Extr., June, 2023
IEEE Open J. Comput. Soc., 2023
ChatGPT at the Speed of Light: Optical Comb-Based Monolithic Photonic-Electronic Linear-Algebra Accelerators.
CoRR, 2023
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Efficient Distribution Similarity Identification in Clustered Federated Learning via Principal Angles between Client Data Subspaces.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2022
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim., 2022
<i>LiteCON</i>: An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning.
ACM Trans. Archit. Code Optim., 2022
Optimizing 3D U-Net-based Brain Tumor Segmentation with Integer-arithmetic Deep Learning Accelerators.
ACM J. Emerg. Technol. Comput. Syst., 2022
IEEE Embed. Syst. Lett., 2022
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Des. Test, 2022
FLIS: Clustered Federated Learning via Inference Similarity for Non-IID Data Distribution.
CoRR, 2022
LiteCON: An All-Photonic Neuromorphic Accelerator for Energy-efficient Deep Learning (Preprint).
CoRR, 2022
Spectrum Pursuit With Residual Descent for Column Subset Selection Problem: Theoretical Guarantees and Applications in Deep Learning.
IEEE Access, 2022
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access, 2022
2021
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst., 2021
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Embed. Syst. Lett., 2021
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
Personalized Federated Learning by Structured and Unstructured Pruning under Data Heterogeneity.
Proceedings of the 41st IEEE International Conference on Distributed Computing Systems Workshops, 2021
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding.
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Select to Better Learn: Fast and Accurate Deep Learning Using Data Selection From Nonlinear Manifolds.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2019
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems.
ACM Trans. Design Autom. Electr. Syst., 2019
Smart-Hop Arbitration Request Propagation: Avoiding Quadratic Arbitration Complexity and False Negatives in SMART NoCs.
ACM Trans. Design Autom. Electr. Syst., 2019
A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets.
ACM Trans. Archit. Code Optim., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Uniform Minimal First: Latency Reduction in Throughput-Optimal Oblivious Routing for Mesh-Based Networks-on-Chip.
IEEE Embed. Syst. Lett., 2019
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the 39th IEEE International Conference on Distributed Computing Systems, 2019
2018
Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2017
Proc. ACM Meas. Anal. Comput. Syst., 2017
A simple re-sequencing load-balanced switch based on analytical packet reordering bounds.
Proceedings of the 2017 IEEE Conference on Computer Communications, 2017
Improving Backpressure-based Adaptive Routing via Incremental Expansion of Routing Choices.
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2017
2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
Revisiting State Blow-Up: Automatically Building Augmented-FA While Preserving Functional Equivalence.
IEEE J. Sel. Areas Commun., 2014
Sprinklers: A Randomized Variable-Size Striping Approach to Reordering-Free Load-Balanced Switching.
Proceedings of the 10th ACM International on Conference on emerging Networking Experiments and Technologies, 2014
2013
IEEE Trans. Parallel Distributed Syst., 2013
Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling.
IEEE Trans. Parallel Distributed Syst., 2013
ACM Trans. Design Autom. Electr. Syst., 2013
IEEE Trans. Netw. Serv. Manag., 2013
IEEE Trans. Computers, 2013
IEEE Comput. Archit. Lett., 2013
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE/ACM Trans. Netw., 2012
Measurement-Aware Monitor Placement and Routing: A Joint Optimization Approach for Network-Wide Measurements.
IEEE Trans. Netw. Serv. Manag., 2012
Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing.
IEEE Trans. Computers, 2012
An Oblivious Routing Algorithm for 3D Mesh Networks to Achieve a New Worst-Case Throughput Bound.
IEEE Embed. Syst. Lett., 2012
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Distributed measurement-aware routing: Striking a balance between measurement and traffic engineering.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012
Oblivious routing design for mesh networks to achieve a new worst-case throughput bound.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011
IEEE/ACM Trans. Netw., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 19th International Workshop on Quality of Service, 2011
Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011
2010
IEEE Trans. Netw. Serv. Manag., 2010
Comput. Commun., 2010
Proceedings of the Passive and Active Measurement, 11th International Conference, 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the INFOCOM 2010. 29th IEEE International Conference on Computer Communications, 2010
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 11th IEEE International Conference on High Performance Switching and Routing, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE/ACM Trans. Netw., 2009
A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.
SIGMETRICS Perform. Evaluation Rev., 2009
IET Comput. Digit. Tech., 2009
IEEE Comput. Archit. Lett., 2009
Proceedings of the 17th International Workshop on Quality of Service, 2009
Proceedings of the 17th International Workshop on Quality of Service, 2009
Design and performance analysis of a DRAM-based statistics counter array architecture.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009
A block-based reservation architecture for the implementation of large packet buffers.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009
2008
SIGMETRICS Perform. Evaluation Rev., 2008
J. Electr. Comput. Eng., 2008
EURASIP J. Embed. Syst., 2008
IEEE Comput. Archit. Lett., 2008
Proceedings of the 16th annual IEEE International Conference on Network Protocols, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the 2007 Workshop on Large Scale Attack Defense, 2007
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007
2006
Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005
2004
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004
2000
Proceedings of the Proceedings IEEE INFOCOM 2000, 2000
Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000
1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 1998 Design, 1998
Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling.
Proceedings of the 1998 Design, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Des. Autom. Embed. Syst., 1997
Derivation of Formal Representations from Process-Based Specification and Implementation Models.
Proceedings of the 10th International Symposium on System Synthesis, 1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 33st Conference on Design Automation, 1996
A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures.
Proceedings of the 33st Conference on Design Automation, 1996
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications.
Proceedings of the 33st Conference on Design Automation, 1996
A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications.
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Background memory management for dynamic data structure intensive processing systems.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Symbolic hazard-free minimization and encoding of asynchronous finite state machines.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995
1994
A generalized state assignment theory for transformations on signal transition graphs.
J. VLSI Signal Process., 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Synthesis of concurrent system interface modules with automatic protocol conversion generation.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the 31st Conference on Design Automation, 1994
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
A generalized state assignment theory for transformation on signal transition graphs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Exact Redundant State Registers Removal Based on Binary Decision Diagrams.
Proceedings of the VLSI 91, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
1987
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987