Bill Lin

Orcid: 0000-0003-0965-7247

Affiliations:
  • University of California at San Diego, Department of Electrical and Computer Engineering, La Jolla, USA


According to our database1, Bill Lin authored at least 191 papers between 1987 and 2024.

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Bibliography

2024
A Practical Recipe for Federated Learning Under Statistical Heterogeneity Experimental Design.
IEEE Trans. Artif. Intell., April, 2024

Rethinking Data Heterogeneity in Federated Learning: Introducing a New Notion and Standard Benchmarks.
IEEE Trans. Artif. Intell., March, 2024

Towards Diverse Device Heterogeneous Federated Learning via Task Arithmetic Knowledge Integration.
CoRR, 2024

Micro-Ring Modulator Linearity Enhancement for Analog and Digital Optical Links.
CoRR, 2024

Stable Diffusion-based Data Augmentation for Federated Learning with Non-IID Data.
CoRR, 2024

On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations.
CoRR, 2024

Monolithic Silicon-Photonics Linear-Algebra Accelerators Enabling Next-Gen Massive MIMO.
CoRR, 2024

2023
Rethinking Logic Minimization for Tabular Machine Learning.
IEEE Trans. Artif. Intell., October, 2023

DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Alternative Formulations of Decision Rule Learning from Neural Networks.
Mach. Learn. Knowl. Extr., June, 2023

Disjunctive Threshold Networks for Tabular Data Classification.
IEEE Open J. Comput. Soc., 2023

FLIS: Clustered Federated Learning Via Inference Similarity for Non-IID Data Distribution.
IEEE Open J. Comput. Soc., 2023

ChatGPT at the Speed of Light: Optical Comb-Based Monolithic Photonic-Electronic Linear-Algebra Accelerators.
CoRR, 2023

Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration.
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies.
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

When Do Curricula Work in Federated Learning?
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Efficient Distribution Similarity Identification in Clustered Federated Learning via Principal Angles between Client Data Subspaces.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2022

SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim., 2022

<i>LiteCON</i>: An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning.
ACM Trans. Archit. Code Optim., 2022

Optimizing 3D U-Net-based Brain Tumor Segmentation with Integer-arithmetic Deep Learning Accelerators.
ACM J. Emerg. Technol. Comput. Syst., 2022

Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Embed. Syst. Lett., 2022

JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Des. Test, 2022

Neural Routing in Meta Learning.
CoRR, 2022

NeuCASL: From Logic Design to System Simulation of Neuromorphic Engines.
CoRR, 2022

LiteCON: An All-Photonic Neuromorphic Accelerator for Energy-efficient Deep Learning (Preprint).
CoRR, 2022

Spectrum Pursuit With Residual Descent for Column Subset Selection Problem: Theoretical Guarantees and Applications in Deep Learning.
IEEE Access, 2022

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access, 2022

2021
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC.
IEEE Embed. Syst. Lett., 2021

Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

Unsupervised Meta-Learning through Latent-Space Interpolation in Generative Models.
Proceedings of the 9th International Conference on Learning Representations, 2021

Personalized Federated Learning by Structured and Unstructured Pruning under Data Heterogeneity.
Proceedings of the 41st IEEE International Conference on Distributed Computing Systems Workshops, 2021

CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Learning Accurate and Interpretable Decision Rule Sets from Neural Networks.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding.
ACM Trans. Archit. Code Optim., 2020

Differentially-private Federated Neural Architecture Search.
CoRR, 2020

MEMTONIC: A Neuromorphic Accelerator for Energy Efficient Deep Learning.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Select to Better Learn: Fast and Accurate Deep Learning Using Data Selection From Nonlinear Manifolds.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Efficient Traffic Load-Balancing via Incremental Expansion of Routing Choices.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2019

Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems.
ACM Trans. Design Autom. Electr. Syst., 2019

Smart-Hop Arbitration Request Propagation: Avoiding Quadratic Arbitration Complexity and False Negatives in SMART NoCs.
ACM Trans. Design Autom. Electr. Syst., 2019

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets.
ACM Trans. Archit. Code Optim., 2019

Trained Biased Number Representation for ReRAM-Based Neural Network Accelerators.
ACM J. Emerg. Technol. Comput. Syst., 2019

Uniform Minimal First: Latency Reduction in Throughput-Optimal Oblivious Routing for Mesh-Based Networks-on-Chip.
IEEE Embed. Syst. Lett., 2019

ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Strengthening the Positive Effect of Viral Marketing.
Proceedings of the 39th IEEE International Conference on Distributed Computing Systems, 2019

2018
Network Optimization for Unified Packet and Circuit Switched Networks.
CoRR, 2018

Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

SARA: self-aware resource allocation for heterogeneous MPSoCs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2017

Safe Randomized Load-Balanced Switching By Diffusing Extra Loads.
Proc. ACM Meas. Anal. Comput. Syst., 2017

A simple re-sequencing load-balanced switch based on analytical packet reordering bounds.
Proceedings of the 2017 IEEE Conference on Computer Communications, 2017

Improving Backpressure-based Adaptive Routing via Incremental Expansion of Routing Choices.
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2017

2016
Sharing a global on-chip transmission line medium without centralized scheduling.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
LEISURE: Load-Balanced Network-Wide Traffic Measurement and Monitor Placement.
IEEE Trans. Parallel Distributed Syst., 2015

ORION3.0: A Comprehensive NoC Router Estimation Tool.
IEEE Embed. Syst. Lett., 2015

2014
Reservation-Based Packet Bufferswith Deterministic Packet Departures.
IEEE Trans. Parallel Distributed Syst., 2014

Revisiting State Blow-Up: Automatically Building Augmented-FA While Preserving Functional Equivalence.
IEEE J. Sel. Areas Commun., 2014

Resistive Computation: A Critique.
IEEE Comput. Archit. Lett., 2014

Sprinklers: A Randomized Variable-Size Striping Approach to Reordering-Free Load-Balanced Switching.
Proceedings of the 10th ACM International on Conference on emerging Networking Experiments and Technologies, 2014

2013
Robust Statistics Counter Arrays with Interleaved Memories.
IEEE Trans. Parallel Distributed Syst., 2013

Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling.
IEEE Trans. Parallel Distributed Syst., 2013

Destination-based congestion awareness for adaptive routing in 2D mesh networks.
ACM Trans. Design Autom. Electr. Syst., 2013

Guest Editors' Introduction: Special Issue on Quality-of-Service.
IEEE Trans. Netw. Serv. Manag., 2013

Randomized Throughput-Optimal Oblivious Routing for Torus Networks.
IEEE Trans. Computers, 2013

A New Worst-Case Throughput Bound for Oblivious Routing in Odd Radix Mesh Network.
IEEE Comput. Archit. Lett., 2013

High-dimensional metamodeling for prediction of clock tree synthesis outcomes.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Enhanced metamodeling techniques for high-dimensional IC design estimation problems.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

DRAM-Based Statistics Counter Array Architecture With Performance Guarantee.
IEEE/ACM Trans. Netw., 2012

Measurement-Aware Monitor Placement and Routing: A Joint Optimization Approach for Network-Wide Measurements.
IEEE Trans. Netw. Serv. Manag., 2012

Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing.
IEEE Trans. Computers, 2012

An Oblivious Routing Algorithm for 3D Mesh Networks to Achieve a New Worst-Case Throughput Bound.
IEEE Embed. Syst. Lett., 2012

An on-chip global broadcast network design with equalized transmission lines in the 1024-core era.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Distributed measurement-aware routing: Striking a balance between measurement and traffic engineering.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012

Oblivious routing design for mesh networks to achieve a new worst-case throughput bound.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Explicit modeling of control and data for improved NoC router estimation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Design of Application-Specific 3D Networks-on-Chip Architectures.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

BRICK: a novel exact active statistics counter architecture.
IEEE/ACM Trans. Netw., 2011

Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Designing efficient codes for synchronization error channels.
Proceedings of the 19th International Workshop on Quality of Service, 2011

Per-flow Queue Scheduling with Pipelined Counting Priority Index.
Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011

LEISURE: A Framework for Load-Balanced Network-Wide Traffic Measurement.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010
The Concurrent Matching Switch Architecture.
IEEE/ACM Trans. Netw., 2010

The taming of the shrew: mitigating low-rate TCP-targeted attack.
IEEE Trans. Netw. Serv. Manag., 2010

Frame-based multicast switching.
IEEE Commun. Lett., 2010

Birkhoff-von Neumann switching with statistical traffic profiles.
Comput. Commun., 2010

Network DVR: A Programmable Framework for Application-Aware Trace Collection.
Proceedings of the Passive and Active Measurement, 11th International Conference, 2010

Design of a High-Throughput Distributed Shared-Buffer NoC Router.
Proceedings of the NOCS 2010, 2010

Design and Analysis of a Robust Pipelined Memory System.
Proceedings of the INFOCOM 2010. 29th IEEE International Conference on Computer Communications, 2010

Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Block-based packet buffer with deterministic packet departures.
Proceedings of the 11th IEEE International Conference on High Performance Switching and Routing, 2010

Trace-driven optimization of networks-on-chip configurations.
Proceedings of the 47th Design Automation Conference, 2010

Improved on-chip router analytical power and area modeling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Destination-based adaptive routing on 2D mesh networks.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
Custom Networks-on-Chip Architectures With Multicast Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Proactive surge protection: a defense mechanism for bandwidth-based attacks.
IEEE/ACM Trans. Netw., 2009

A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.
SIGMETRICS Perform. Evaluation Rev., 2009

Joint multicast routing and network design optimisation for networks-on-chip.
IET Comput. Digit. Tech., 2009

A Layer-Multiplexed 3D On-Chip Network Architecture.
IEEE Embed. Syst. Lett., 2009

A High-Throughput Distributed Shared-Buffer NoC Router.
IEEE Comput. Archit. Lett., 2009

Weighted Random Routing on Torus Networks.
IEEE Comput. Archit. Lett., 2009

Succinct priority indexing structures for the management of large priority queues.
Proceedings of the 17th International Workshop on Quality of Service, 2009

Optimal multi-path routing and bandwidth allocation under utility max-min fairness.
Proceedings of the 17th International Workshop on Quality of Service, 2009

Design and performance analysis of a DRAM-based statistics counter array architecture.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

A block-based reservation architecture for the implementation of large packet buffers.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

A novel 3D layer-multiplexed on-chip network.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

Weighted random oblivious routing on torus networks.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008
DRAM is plenty fast for wirespeed statistics counting.
SIGMETRICS Perform. Evaluation Rev., 2008

A Simple Mechanism for Throttling High-Bandwidth Flows.
J. Electr. Comput. Eng., 2008

Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures.
EURASIP J. Embed. Syst., 2008

Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks.
IEEE Comput. Archit. Lett., 2008

Rank-indexed hashing: A compact construction of Bloom filters and variants.
Proceedings of the 16th annual IEEE International Conference on Network Protocols, 2008

Design of application-specific 3D Networks-on-Chip architectures.
Proceedings of the 26th International Conference on Computer Design, 2008

Near-optimal oblivious routing on three-dimensional mesh networks.
Proceedings of the 26th International Conference on Computer Design, 2008

Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Compiling concurrent programs for embedded sequential execution.
Integr., 2007

Minimizing collateral damage by proactive surge protection.
Proceedings of the 2007 Workshop on Large Scale Attack Defense, 2007

Stream execution on wide-issue clustered VLIW architectures.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Pipelined van Emde Boas Tree: Algorithms, Analysis, and Applications.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

Frame-aggregated concurrent matching switch.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006
Fast Buffer Memory with Deterministic Packet Departures.
Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006

On the Efficient Implementation of Pipelined Heaps for Network Processing.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
On the impact of traffic statistics on quality of service for networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Scalable Switch for Service Guarantees.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

2004
Maintaining exact statistics counters with a multi-level counter memory.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2000
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches.
Proceedings of the Proceedings IEEE INFOCOM 2000, 2000

Design of High-Speed Packet Switch with Fine-Grained Quality-of-Service Guarantees.
Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000

1999
Compositional Software Synthesis of Communicating Processes.
Proceedings of the IEEE International Conference On Computer Design, 1999

Design and implementation of high-speed symmetric crossbar schedulers.
Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999

Hardware Compilation for FPGA-Based Configurable Computing Machines.
Proceedings of the 36th Conference on Design Automation, 1999

1998
BDD-based synthesis of extended burst-mode controllers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Efficient Verification using Generalized Partial Order Analysis.
Proceedings of the 1998 Design, 1998

Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling.
Proceedings of the 1998 Design, 1998

Software Synthesis of Process-Based Concurrent Programs.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Externally hazard-free implementations of asynchronous control circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Hardware/software co-design of digital telecommunication systems.
Proc. IEEE, 1997

Hardware/Software Communication and System Integration for Embedded Architectures.
Des. Autom. Embed. Syst., 1997

Derivation of Formal Representations from Process-Based Specification and Implementation Models.
Proceedings of the 10th International Symposium on System Synthesis, 1997

A System Design Methodology for Telecommunication Network Applications.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996

Flow Graph Balancing for Minimizing the Required Memory Bandwidth.
Proceedings of the 9th International Symposium on System Synthesis, 1996

System design tools for broadband telecom network applications.
Proceedings of the 1996 European Design and Test Conference, 1996

Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems.
Proceedings of the 33st Conference on Design Automation, 1996

A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures.
Proceedings of the 33st Conference on Design Automation, 1996

Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications.
Proceedings of the 33st Conference on Design Automation, 1996

A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications.
Proceedings of the 33st Conference on Design Automation, 1996

Embedded Architecture Co-Synthesis and System Integration.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

Control resynthesis for control-dominated asynchronous designs.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Power estimation methods for sequential logic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Efficient state assignment framework for asynchronous state graphs.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Background memory management for dynamic data structure intensive processing systems.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Symbolic hazard-free minimization and encoding of asynchronous finite state machines.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Modeling and optimization of hierarchical synchronous circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

Externally Hazard-Free Implementations of Asynchronous Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Hierarchical Optimization of Asynchronous Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Optimised state assignment for asynchronous circuit synthesis.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Algorithms for the optimal state assignment of asynchronous state machines.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
A generalized state assignment theory for transformations on signal transition graphs.
J. VLSI Signal Process., 1994

Performance-driven synthesis of asynchronous controllers.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of concurrent system interface modules with automatic protocol conversion generation.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Design of heterogeneous ICs for mobile and personal communication systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Generalized Signal Transition Graph Model for Specification of Complex Interfaces.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A general state graph transformation framework for asynchronous synthesis.
Proceedings of the Proceedings EURO-DAC'94, 1994

A Time Abstraction Method for Efficient Verification of Communicating Systems.
Proceedings of the 31st Conference on Design Automation, 1994

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Basic Gate Implementation of Speed-Independent Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Low-Power Driven Technology Mapping under Timing Constraints.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Efficient Symbolic Support Manipulation.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Sizing and verification of communication buffers for communicating processes.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A generalized state assignment theory for transformation on signal transition graphs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Communication based logic partitioning.
Proceedings of the conference on European design automation, 1992

Symbolic Prime Generation for Multiple-Valued Functions.
Proceedings of the 29th Design Automation Conference, 1992

1991
MUSE: a multilevel symbolic encoding algorithm for state assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Exact Redundant State Registers Removal Based on Binary Decision Diagrams.
Proceedings of the VLSI 91, 1991

Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Implicit State Enumeration of Finite State Machines Using BDDs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Don't Care Minimization of Multi-Level Sequential Logic Networks.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Minimization of Symbolic Relations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
A generalized approach to the constrained cubical embedding problem.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1987
KAHLUA: A Hierarchical Circuit Disassembler.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987


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