Biju K. Raveendran

Orcid: 0000-0003-0749-0295

According to our database1, Biju K. Raveendran authored at least 22 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
CAMP: a hierarchical cache architecture for multi-core mixed criticality processors.
Int. J. Parallel Emergent Distributed Syst., May, 2024

2023
mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems.
Int. J. Parallel Emergent Distributed Syst., September, 2023

SACRED: Software Approach for Collaboration and Research Dissemination.
Int. J. e Collab., 2023

Task models for mixed criticality systems - a review.
Int. J. Crit. Comput. Based Syst., 2023

2021
pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021

MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache.
Proceedings of the 25th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2021

2019
MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation.
Int. J. Embed. Syst., 2019

DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems.
Int. J. Embed. Syst., 2019

MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems.
Proceedings of the 23rd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications DS-RT 2019, 2019

2018
SMILEY: A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems.
Proceedings of the 22nd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2018

2017
LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors.
Sustain. Comput. Informatics Syst., 2017

Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors.
Int. J. Embed. Syst., 2017

eduCloud: a VM communication aware, migration efficient cloud for scientific computing.
Int. J. Commun. Networks Distributed Syst., 2017

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016
DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems.
Proceedings of the International Conference on Control, 2016

2015
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors.
Proceedings of the 28th International Conference on VLSI Design, 2015

Simulation based Performance Study of Cache Coherence Protocols.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2008
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

2007
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

EFFS: Efficient Flash File System for Wireless Sensor Nodes.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems.
Proceedings of the Distributed Computing and Networking, 8th International Conference, 2006

A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006


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