Bijan Davari
According to our database1,
Bijan Davari
authored at least 6 papers
between 1995 and 2010.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2002, "For contributions to high performance deep-submicron CMOS technology development.".
Timeline
1996
1998
2000
2002
2004
2006
2008
2010
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2010
2000
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
IEEE J. Solid State Circuits, 2000
1998
A 480-MHz RISC microprocessor in a 0.12-μm L<sub>eff</sub> CMOS technology with copper interconnects.
IEEE J. Solid State Circuits, 1998
1995
IBM J. Res. Dev., 1995