Bijan Alizadeh

Orcid: 0000-0003-4436-4597

According to our database1, Bijan Alizadeh authored at least 94 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Systematic Trojan Detection in Crypto-Systems Using the Model Checker.
J. Circuits Syst. Comput., February, 2024

Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification.
ACM Trans. Design Autom. Electr. Syst., 2024

An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection.
IEEE Trans. Instrum. Meas., 2024

2023
DC-PUF: Machine learning-resistant PUF-based authentication protocol using dependency chain for resource-constraint IoT devices.
J. Netw. Comput. Appl., 2023

Automatic correction of RTL designs using a lightweight partial high level synthesis.
Integr., 2023

2022
A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things.
Microprocess. Microsystems, September, 2022

Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices.
ISC Int. J. Inf. Secur., 2022

2021
Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

FPGA-based Implementation of a New Data Frame Correction System for Merging Units.
CoRR, 2021

Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits.
IEEE Trans. Circuits Syst., 2020

PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices.
J. Netw. Comput. Appl., 2020

2019
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors.
IEEE Trans. Instrum. Meas., 2019

Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Data-path aware high-level ECO synthesis.
Integr., 2019

A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification.
Proceedings of the 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, 2019

2018
Automatic Correction of Dynamic Power Management Architecture in Modern Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

2017
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2017

OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2017

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Systematic Design Space Exploration of Floating-Point Expressions on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Improved Range Analysis in Fixed-Point Polynomial Data-Path.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs.
CoRR, 2017

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Systematic approximate logic optimization using don't care conditions.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models.
ACM Trans. Design Autom. Electr. Syst., 2016

UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A dynamic specification to automatically debug and correct various divider circuits.
Integr., 2016

Combinational trace signal selection with improved state restoration for post-silicon debug.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formally analyzing fault tolerance in datapath designs using equivalence checking.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition.
IEEE Trans. Computers, 2015

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.
IEEE Trans. Computers, 2015

Analytical performance model for FPGA-based reconfigurable computing.
Microprocess. Microsystems, 2015

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction.
Microprocess. Microsystems, 2015

UPF-based formal verification of low power techniques in modern processors.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Signature oriented model pruning to facilitate multi-threaded processors debugging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Timing Error Mitigation Technique for High Performance Designs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Low power scheduling in high-level synthesis using dual-Vth library.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

RTL datapath optimization using system-level transformations.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Improving polynomial datapath debugging with HEDs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Automatic correction of certain design errors using mutation technique.
Proceedings of the 19th IEEE European Test Symposium, 2014

Automated formal approach for debugging dividers using dynamic specification.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Dynamic Flip-Flop conversion to tolerate process variation in low power circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs.
Microprocess. Microsystems, 2013

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits.
IEEE Des. Test, 2013

A probabilistic approach for counterexample generation to aid design debugging.
Proceedings of the East-West Design & Test Symposium, 2013

2012
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors.
ACM Trans. Design Autom. Electr. Syst., 2012

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2<sup>m</sup> and algebraic techniques.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

A functional test generation technique for RTL datapaths.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

A formal approach to debug polynomial datapath designs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Early case splitting and false path detection to improve high level ATPG techniques.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Modular equivalence verification of polynomial datapaths with multiple word-length operands.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Modular Datapath Optimization and Verification Based on Modular-HED.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Polynomial datapath optimization using constraint solving and formal modelling.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A debugging method for repairing post-silicon bugs of high performance processors in the fields.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Guided gate-level ATPG for sequential circuits using a high-level test generation approach.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Pipelined Microprocessors Optimization and Debugging.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
A Formal Approach for Debugging Arithmetic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Unified Framework for Equivalence Verification of Datapath Oriented Applications.
IEICE Trans. Inf. Syst., 2009

High-level optimization of integer multipliers over a finite bit-width with verification capabilities.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Improved heuristics for finite word-length polynomial datapath optimization.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Modular arithmetic decision procedure with auto-correction mechanism.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Polynomial datapath optimization using partitioning and compensation heuristics.
Proceedings of the 46th Design Automation Conference, 2009

2008
Arithmetic Circuits Verification without Looking for Internal Equivalences.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
A novel formal approach to generate high-level test vectors without ILP and SAT solvers.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.
Proceedings of the Automated Technology for Verification and Analysis, 2007

2006
Word level functional coverage computation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Using Integer Equations to Check PSL Properties in RT Level Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Property Checking based on Hierarchical Integer Equations.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003
Using Integer Equations for High Level Formal Verification Property Checking.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003


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