Bibhash Sen
Orcid: 0000-0003-4803-3074Affiliations:
- National Institute of Technology Durgapur, Department of Computer Science and Engineering, India
According to our database1,
Bibhash Sen
authored at least 64 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on orcid.org
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on nitdgp.ac.in
On csauthors.net:
Bibliography
2024
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm.
J. Electron. Test., June, 2024
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency.
Integr., March, 2024
Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network.
ACM J. Emerg. Technol. Comput. Syst., January, 2024
J. Circuits Syst. Comput., 2024
Proceedings of the Cellular Automata Technology - Third Asian Symposium, 2024
2023
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity.
ACM J. Emerg. Technol. Comput. Syst., October, 2023
Biomed. Signal Process. Control., August, 2023
PLAKE: PUF-Based Secure Lightweight Authentication and Key Exchange Protocol for IoT.
IEEE Internet Things J., May, 2023
J. Supercomput., March, 2023
ACM Trans. Embed. Comput. Syst., 2023
Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach.
Biomed. Signal Process. Control., 2023
Proceedings of Second Asian Symposium on Cellular Automata Technology, 2023
2022
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT.
ACM Trans. Design Autom. Electr. Syst., 2022
PUF based Secure and Lightweight Authentication and Key-Sharing Scheme for Wireless Sensor Network.
ACM J. Emerg. Technol. Comput. Syst., 2022
Towards the realization of regular clocking-based QCA circuits using genetic algorithm.
Comput. Electr. Eng., 2022
Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit.
Comput. Electr. Eng., 2022
A Novel Cross-Platform Physically Unclonable Function for Emerging FPGA-based IoT Devices.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
Proceedings of First Asian Symposium on Cellular Automata Technology, 2022
Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach.
Proceedings of the Cellular Automata, 2022
2021
CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability.
J. Circuits Syst. Comput., 2021
Systematic cell placement in quantum-dot cellular automata embedding underlying regular clocking circuit.
IET Circuits Devices Syst., 2021
J. Electron. Test., 2021
Proceedings of the 18th International Conference on Security and Cryptography, 2021
2020
Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic.
Int. J. Comput. Sci. Eng., 2020
IET Comput. Digit. Tech., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
J. Electron. Test., 2019
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
2017
Microelectron. J., 2017
Realization of processing In-memory computing architecture using Quantum Dot Cellular Automata.
Microprocess. Microsystems, 2017
Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA.
J. Circuits Syst. Comput., 2017
Int. J. Comput. Appl. Technol., 2017
IET Circuits Devices Syst., 2017
CoRR, 2017
Synthesis and Optimization of Multi-Objective Multi-Output QCA Circuit using Genetic Algorithm.
CoRR, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
2016
Microelectron. J., 2016
CoRR, 2016
Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
2015
J. Comput. Sci., 2015
Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers.
Comput. Electr. Eng., 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing.
Microelectron. J., 2014
Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability.
Microelectron. J., 2014
Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU.
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
2011
Proceedings of the International Symposium on Electronic System Design, 2011
2010
Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings.
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010