Bianca Silveira

According to our database1, Bianca Silveira authored at least 13 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022

Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A power-efficient 4-2 Adder Compressor topology.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Low power sum of absolute differences architecture using novel hybrid adder.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Exploring the use of parallel prefix adder topologies into approximate adder circuits.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Exploiting absolute arithmetic for power-efficient sum of absolute differences.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Power-efficient sum of absolute differences architecture using adder compressors.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


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