Bheemappa Halavar

Orcid: 0000-0003-4776-7180

According to our database1, Bheemappa Halavar authored at least 6 papers between 2018 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of six.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2020
Power and performance analysis of 3D network-on-chip architectures.
Comput. Electr. Eng., 2020

2019
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures.
Simul. Model. Pract. Theory, 2019

2018
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip.
Proceedings of the 2018 International Conference on Signal Processing and Communications (SPCOM), 2018

Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture.
Proceedings of the Intelligent Systems Design and Applications, 2018

Accurate Power and Latency Analysis of a Through-Silicon Via(TSV).
Proceedings of the 2018 International Conference on Advances in Computing, 2018


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