Bheema Rao Nistala

According to our database, Bheema Rao Nistala authored at least 5 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2023

Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation.

Sunitha Bhukya, Bheema Rao Nistala

Microelectron. J., September, 2023

A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET.

Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap.

Praveen Kumar Mudidhe, Bheema Rao Nistala

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2018

Design of an on-chip Hilbert fractal inductor using an improved feed forward neural network for Si RFICs.

Akhendra Kumar Padavala, Bheema Rao Nistala

Turkish J. Electr. Eng. Comput. Sci., 2018

2017

High inductance fractal inductors for wireless applications.

Akhendra Kumar Padavala, Bheema Rao Nistala

Turkish J. Electr. Eng. Comput. Sci., 2017