Bhavan A. Jasani

According to our database, Bhavan A. Jasani authored at least 4 papers between 2018 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector.

Siew-Kei Lam, Teck Chuan Lim, Meiqing Wu, Bin Cao, Bhavan A. Jasani

J. Real Time Image Process., 2019

2018

Threshold-Guided Design and Optimization for Harris Corner Detector Architecture.

Bhavan A. Jasani, Siew-Kei Lam, Pramod Kumar Meher, Meiqing Wu

IEEE Trans. Circuits Syst. Video Technol., 2018

Area-Time Efficient FAST Corner Detector Using Data-Path Transposition.

Siew-Kei Lam, Teck Chuan Lim, Meiqing Wu, Bin Cao, Bhavan A. Jasani

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Stream-Based ORB Feature Extractor with Dynamic Power Optimization.

Phong Tran, Thinh Hung Pham, Siew Kei Lam, Meiqing Wu, Bhavan A. Jasani

Proceedings of the International Conference on Field-Programmable Technology, 2018