Bharath Shankaranarayanan

According to our database, Bharath Shankaranarayanan authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests.

Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora

Proceedings of the IEEE International Test Conference, 2024

2023

Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design Level.

Vinay Kumar, Bhrugurajsinh Chudasama, Bin B. W. Wang, Manish Arora, Bharath Shankaranarayanan

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation.

Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora

Proceedings of the IEEE International Test Conference, 2023

2021

SoC Trust Validation Using Assertion-Based Security Monitors.

Khitam Alatoun, Bharath Shankaranarayanan, Shanmukha Murali Achyutha, Ranga Vemuri

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021