Bharat Choudhary

Orcid: 0000-0002-7311-1815

According to our database1, Bharat Choudhary authored at least 5 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Performance Assessment of High-k SOI GaN FinFET with Different Fin Aspect Ratio for RF/Wireless Applications.
Wirel. Pers. Commun., May, 2024

2018
MCML Dynamic Register Design.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies.
J. Circuits Syst. Comput., 2017

2016
New Proposal for MCML Based Three-Input Logic Implementation.
VLSI Design, 2016

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells.
Microelectron. J., 2016


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