Bhagirath Narahari

According to our database1, Bhagirath Narahari authored at least 57 papers between 1986 and 2015.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2012
Shared hardware data structures for hard real-time systems.
Proceedings of the 12th International Conference on Embedded Software, 2012

No Principal Too Small: Memory Access Control for Fine-Grained Protection Domains.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2010
Detecting memory spoofing in secure embedded systems using cache-aware FPGA guards.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

2009
Providing secure execution environments with a last line of defense against Trojan circuit attacks.
Comput. Secur., 2009

A compiler-hardware approach to software protection for embedded systems.
Comput. Electr. Eng., 2009

OS Support for Detecting Trojan Circuit Attacks.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Hardware-enforced fine-grained isolation of untrusted code.
Proceedings of the First ACM Workshop on Secure Execution of Untrusted Code, 2009

2008
Architectural support for securing application data in embedded systems.
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

2007
Privacy-preserving programming using sython.
Comput. Secur., 2007

Compiler-Directed Region-Based Security for Low-Overhead Software Protection.
Proceedings of the Third IEEE International Symposium on Dependable, 2007

2006
High-Performance Software Protection Using Reconfigurable Architectures.
Proc. IEEE, 2006

SPEE: A Secure Program Execution Environment tool using code integrity checking.
J. High Speed Networks, 2006

Geometric Chemotaxis: A Biologically-Inspired Framework for a Class of Wireless Coverage Problems.
Ad Hoc Sens. Wirel. Networks, 2006

2005
SAFE-OPS: An approach to embedded software security.
ACM Trans. Embed. Comput. Syst., 2005

Performance Study of a Compiler/Hardware Approach to Embedded Systems Security.
Proceedings of the Intelligence and Security Informatics, 2005

CODESSEAL: Compiler/FPGA Approach to Secure Applications.
Proceedings of the Intelligence and Security Informatics, 2005

2004
HomeOS: Context-Aware Home Connectivity.
Proceedings of the International Conference on Wireless Networks, 2004

Flexible Software Protection Using Hardware/Software Codesign Techniques.
Proceedings of the 2004 Design, 2004

2003
Strong Minimum Energy Topology in Wireless Sensor Networks: NP-Completeness and Heuristics.
IEEE Trans. Mob. Comput., 2003

Audio Data Indexing Using Discrete Cosine Transform.
Int. J. Comput. Their Appl., 2003

Energy balance in wireless networks using connection segmentation and range control.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003

2000
Study of link congestion during I/O transfers in 2-D meshes using wormhole routing.
Proceedings of the ISCA 15th International Conference Computers and Their Applications, 2000

1999
Routing and Scheduling I/O Transfers on Wormhole-Routed Mesh Networks.
J. Parallel Distributed Comput., 1999

Fine Grained Register Allocation for EPIC Processors With Predication.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Automated classification of audio data and retrieval based on audio classes.
Proceedings of the Computers and Their Applications (CATA-99), 1999

I/O performance of X-Y routing in 2-D meshes under various node-to-disk assignments.
Proceedings of the Computers and Their Applications (CATA-99), 1999

1998
Dynamic load balancing schemes for computing accessible surface area of protein molecules.
Proceedings of the 5th International Conference On High Performance Computing, 1998

Scheduling I/O transfers in a 2-D mesh with packet deadlines.
Proceedings of the 36th Annual ACM Southeast Regional Conference, 1998

1997
Transform-Based Indexing of Audio Data for Multimedia Databases.
Proceedings of the International Conference on Multimedia Computing and Systems, 1997

Parallel real-time systems: formal specification.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
Efficient algorithms for erasure node placement on slotted dual bus networks.
IEEE/ACM Trans. Netw., 1996

File allocation for a parallel Webserver.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

Syntax and Semantics of PRETSEL - A Specification Language for Parallel Real-Time Systems.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

1995
An Approximation Algorithm for Preemptive Scheduling on Parallel-Task Systems.
SIAM J. Discret. Math., 1995

1994
Optimal Processor Assignment for a Class of Pipelined Computations.
IEEE Trans. Parallel Distributed Syst., 1994

1993
An Efficient Heuristic Scheme for Dynamic Remapping of Parallel Computations.
Parallel Comput., 1993

Efficient Algorithms for Mapping and Partioning a Class of Parallel Computations.
J. Parallel Distributed Comput., 1993

Parallel Computation of Solvent Accessible Surface Area of Protein Molecules.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

Scheduling Independent Tasks of Partitionable Hypercube Multiprocessors.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

3 Parallel computer architectures.
Proceedings of the Computational Statistics., 1993

1992
Mapping Binary Precedence Trees to Hypercubes.
Parallel Process. Lett., 1992

Optimal Subcube Assignment for Partitionable Hypercubes.
Parallel Process. Lett., 1992

Topological Properties of Generalized Banyan-Hypercube Networks.
J. Parallel Distributed Comput., 1992

Optimal Embedding of 2-D Torus Into Ring.
Inf. Process. Lett., 1992

Mapping a Chain Task to Chained Processors.
Inf. Process. Lett., 1992

Single Path Routing with Delay Considerations.
Comput. Networks ISDN Syst., 1992

Preemptive Scheduling of Independent Jobs on Partitionable Parallel Architectures.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

1991
Allocating Partitions to Task Precedence Graphs.
Proceedings of the International Conference on Parallel Processing, 1991

Algorithms for Mapping and Partitioning Chain Structured Parallel Computations.
Proceedings of the International Conference on Parallel Processing, 1991

1990
The Banyan-Hypercube Networks.
IEEE Trans. Parallel Distributed Syst., 1990

Mapping binary precedence trees to hypercubes and meshes.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

Scheduling precedence graphs to minimize total system time in partitionable parallel architectures.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

Scheduling on Parallel Processing Systems Using Parallel Primitives.
Proceedings of the Parallel Architectures (Postconference PARBASE-90)., 1990

1989
A software environment of architecture prototypes for evaluating parallel vision systems and algorithms.
Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989

1986
Optimal Mappings among Interconnection Networks for Performance Evaluation.
Proceedings of the 6th International Conference on Distributed Computing Systems, 1986


  Loading...