Bevan M. Baas
Affiliations:- University of California, Davis, USA
According to our database1,
Bevan M. Baas
authored at least 75 papers
between 1998 and 2023.
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Bibliography
2023
Integr., 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
2022
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop.
J. Signal Process. Syst., 2020
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop.
J. Signal Process. Syst., 2020
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array.
J. Parallel Distributed Comput., 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81].
Integr., 2019
2018
A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Micro, 2017
IEEE J. Solid State Circuits, 2017
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm.
Integr., 2017
A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017
2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
2015
Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Area efficient backprojection computation with reduced floating-point word width for SAR image formation.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Hybrid floating-point modules with low area overhead on a fine-grained processing core.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
VLSI Design, 2013
IEEE Trans. Computers, 2013
2012
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
2011
IEEE Trans. Circuits Syst. Video Technol., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
J. Signal Process. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE J. Solid State Circuits, 2009
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of IEEE International Conference on Communications, 2009
2008
J. Signal Process. Syst., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
A complete real-time 802.11a baseband receiver implemented on an array of programmable processors.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. Very Large Scale Integr. Syst., 2007
EURASIP J. Embed. Syst., 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006
2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
1999
IEEE J. Solid State Circuits, 1999
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998