Bertrand Le Gal

, 2023

2022

Methodology to Adapt Neural Network on Constrained Device at Topology level.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

Efficient LoRa-like Transmitter Stacks for SDR Applications.

[BibT_eX]

[DOI]

Léa Volpin

Guillaume Ferré

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

High-throughput FFT architectures using HLS tools.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Efficient Software and Hardware Implementations of a QCSP Communication System.

[BibT_eX]

[DOI]

Camille Monière

Emmanuel Boutillon

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices.

[BibT_eX]

[DOI]

Vincent Pignoly

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

Flexible design methodology for spike encoding implementation on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021

Time sliding window for the detection of CCSK frames.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Extended RISC-V hardware architecture for future digital communication systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE 5G World Forum, 2021

2020

High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Model-based Design of Hardware SC Polar Decoders for FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

Low-latency and high-throughput software turbo decoders on multi-core architectures.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2020

Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

High speed LDPC decoding for optical space link.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Fair comparison of hardware and software LDPC decoder implementations for SDR space links.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

AFF3CT: A Fast Forward Error Correction Toolbox!

[BibT_eX]

[DOI]

SoftwareX, 2019

Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018

Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2018

High-performance software implementations of SCAN decoder for polar codes.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2018

Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

ADMM hardware decoder for regular LDPC codes using a NISC-based architecture.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

High data rate and flexible hardware QC-LDPC decoder for satellite optical communications.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Model-based Design of Efficient LDPC Decoder Architectures.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Hardware design of Euclidean Projection modules for ADMM LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A scalable and efficient digital signal processing system for real time biological spike detection.

[BibT_eX]

[DOI]

Safouane Noubir

Yannick Bornat

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Software, 2017

Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Successive cancellation decoder for very long polar codes.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Low-latency software LDPC decoders for x86 multi-core devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017

An LP-based algorithm for decoding terminated LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Internet of Things, 2017

2016

Lowering the Error Floor of Turbo Codes With CRC Verification.

[BibT_eX]

[DOI]

IEEE Wirel. Commun. Lett., 2016

Real Time LP Decoding of LDPC Codes for High Correction Performance Applications.

[BibT_eX]

[DOI]

IEEE Wirel. Commun. Lett., 2016

A Flexible SoC and Its Methodology for Parser-Based Applications.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2016

High-Throughput Multi-Core LDPC Decoders Based on x86 Processor.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Fast Converging ADMM-Penalized Algorithm for LDPC Decoding.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2016

Evaluation of the hardware complexity of the ADMM approach for LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Wireless Communications and Networking Conference, 2016

Lowering the error floor of double-binary turbo codes: The flip and check algorithm.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Comparison of different schedulings for the ADMM based LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Beyond Gbps Turbo decoder on multi-core CPUs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

A scalable 3-phase polar decoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Memory reduction techniques for successive cancellation decoding of polar codes.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Multicore implementation of LDPC decoders based on ADMM algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Energy consumption analysis of software polar decoders on low power processors.

[BibT_eX]

[DOI]

Proceedings of the 24th European Signal Processing Conference, 2016

Hardware architecture for lowering the error floor of LTE turbo codes.

[BibT_eX]

[DOI]

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015

Multi-Gb/s Software Decoding of Polar Codes.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2015

High-Throughput LDPC Decoder on Low-Power Embedded Processors.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2015

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2015

Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

A Flexible NISC-Based LDPC Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2014

GPU-like on-chip system for decoding LDPC codes.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices.

[BibT_eX]

[DOI]

Jérémie Crenne

IEEE Embed. Syst. Lett., 2014

Software polar decoder on an embedded processor.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

2013

A Very High Throughput Deblocking Filter for H.264/AVC.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Méthodologie d'optimisation des processeurs embarqués. Une approche favorisant la réduction de la surface et de la consommation des processeurs embarqués.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2013

Design space exploration for partially reconfigurable architectures in real-time systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Softcore Processor Optimization According to Real-Application Requirements.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

Improving the performance of message parsers for embedded systems.

[BibT_eX]

[DOI]

Tegawendé F. Bissyandé

Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

2012

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers.

[BibT_eX]

[DOI]

VLSI Design, 2012

Design of multi-mode application-specific cores based on high-level synthesis.

[BibT_eX]

[DOI]

Integr., 2012

Zebra: Building Efficient Network Message Parsers for Embedded Systems.

[BibT_eX]

[DOI]

Tegawendé F. Bissyandé

Jigar Solanki

IEEE Embed. Syst. Lett., 2012

Automatic low-cost IP watermarking technique based on output mark insertions.

[BibT_eX]

[DOI]

Lilian Bossuet

Des. Autom. Embed. Syst., 2012

FPGA based system for automatic cDNA microarray image processing.

[BibT_eX]

[DOI]

Comput. Medical Imaging Graph., 2012

Spatial downsizing impact in the transrating tradeoff for content/context awareness in media network.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Telecommunications and Multimedia, 2012

Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A generic video adaptation framework towards content-and context-awareness in future networks.

[BibT_eX]

[DOI]

Proceedings of the 20th European Signal Processing Conference, 2012

FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard.

[BibT_eX]

[DOI]

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

A generic video adaptation FPGA implementation towards content- and context-awareness in future networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2011

FPGA technology and parallel computing towards automatic microarray image processing.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on Telecommunications and Signal Processing (TSP 2011), 2011

A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems.

[BibT_eX]

[DOI]

Jean-Philippe Delahaye

Dominique Dallet

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A system aproach for reducing power consumption of multimedia devices with a low QoE impact.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Assertion support in high-level synthesis design flow.

[BibT_eX]

[DOI]

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Reducing and smoothing power consumption of ROM-based controller implementations.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A low-area filter bank design methodology for on-chip ADC testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Area optimization of ROM-based controllers dedicated to digital signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

2009

Design and implementation of a reconfigurable decimation and channel selection filter for GSM and UMTS radio standards.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009

High-level synthesis for the design of FPGA-based signal processing systems.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets.

[BibT_eX]

[DOI]

Proceedings of the 17th European Signal Processing Conference, 2009

Automated multimode system design for high performance DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 17th European Signal Processing Conference, 2009

2008

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.

[BibT_eX]

[DOI]

Sylvain Huet

IEEE Trans. Very Large Scale Integr. Syst., 2008

Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.

[BibT_eX]

[DOI]