Bernhard Wicht

Orcid: 0000-0003-0066-2955

According to our database1, Bernhard Wicht authored at least 50 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs.
IEEE J. Solid State Circuits, February, 2024

A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs.
Proceedings of the 20th International Conference on Synthesis, 2024

31.10 A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures.
Proceedings of the 19th International Conference on Synthesis, 2023

A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 2-8V Vin 670mA Scalable Multi-Ratio SC DCDC Converter for MCU Integration in 28nm CMOS Achieving 91% Peak Efficiency.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer.
IEEE J. Solid State Circuits, 2022

A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Resonant One-Step 325 V to 3.3-10 V DC-DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques.
IEEE J. Solid State Circuits, 2021

Session 33 Overview: High-Voltage, GaN and Wireless Power Power Management Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency.
IEEE J. Solid State Circuits, 2020

11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers: Invited Paper.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019

A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500μA -to-120mA Load Range.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 48-V Wide-V<sub>in</sub> 9-25-MHz Resonant DC-DC Converter.
IEEE J. Solid State Circuits, 2018

Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN Transistors.
IEEE J. Solid State Circuits, 2018

A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications.
IEEE J. Solid State Circuits, 2018

F6: Advances in energy efficient analog design.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A fully integrated DC to 75 MHz current sensing circuit with on-chip Rogowski coil.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Time-domain ramped gate sensing for embedded multi-level flash in automotive applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 12-48 V wide-vin 9-15 MHz soft-switching controlled resonant DCDC converter.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control.
IEEE J. Solid State Circuits, 2016

A 40V current sensing circuit with fast on/off transition for high-voltage power management.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing.
IEEE J. Solid State Circuits, 2015

A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain.
Proceedings of the ESSCIRC Conference 2015, 2015

EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015

2014
A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters.
Proceedings of the ESSCIRC 2014, 2014

Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems.
Proceedings of the ESSCIRC 2014, 2014

2013
Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

EMC analysis of current source gate drivers.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2011
EMC influence of the charge pump in linear regulators - Design, simulation and measurements.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay.
IEEE J. Solid State Circuits, 2008

2007
A configurable High-Side/ low-Side Driver.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2004
Yield and speed optimization of a latch-type voltage sense amplifier.
IEEE J. Solid State Circuits, 2004

2003
A yield-optimized latch-type SRAM sense amplifier.
Proceedings of the ESSCIRC 2003, 2003

2001
Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers.
IEEE J. Solid State Circuits, 2001


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