Bernhard Wess

According to our database1, Bernhard Wess authored at least 15 papers between 1994 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2006
Design Methods for DSP Systems.
EURASIP J. Adv. Signal Process., 2006

2005
Integrated assignment of registers and functional units for heterogeneous vliw-architectures.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004
On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Optimum address pointer assignment for digital signal processors.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures.
Signal Process., 2003

Optimum register assignment for heterogeneous register-set architectures.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Minimization of Data Address Computation Overhead in DSP Programs.
Des. Autom. Embed. Syst., 1999

Dynamic trellis diagrams for optimized DSP code generation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Operation scheduling for parallel functional units using genetic algorithms.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998
Minimization of data address computation overhead in DSP programs.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
Constructing memory layouts for address generation units supporting offset 2 access.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Cooperative register assignment and code compaction for digital signal processors with irregular datapaths.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1994
Code generation based on trellis diagrams.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994


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