Bernhard Jungk

According to our database1, Bernhard Jungk authored at least 24 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Serialized lightweight SHA-3 FPGA implementations.
Microprocess. Microsystems, 2019

XMSS and Embedded Systems.
Proceedings of the Selected Areas in Cryptography - SAC 2019, 2019

2018
Efficient Side-Channel Protections of ARX Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V.
IACR Cryptol. ePrint Arch., 2018

Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Feature Selection Methods for Non-Profiled Side-Channel Attacks on ECC.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

On Comparing Side-channel Properties of AES and ChaCha20 on Microcontrollers.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
There Goes Your PIN: Exploiting Smartphone Sensor Fusion Under Single and Cross User Setting.
IACR Cryptol. ePrint Arch., 2017

Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
FPGA-based evaluation of cryptographic algorithms.
PhD thesis, 2016

Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

There ain't no plain key: A PUF based first-order side-channel resistant encryption construction.
Proceedings of the International Symposium on Integrated Circuits, 2016

Automotive security state of the art and future challenges.
Proceedings of the International Symposium on Integrated Circuits, 2016

2014
A systematic study of lightweight hash functions on FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

On a FPGA-based method for authentication using Edwards curves.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

2012
Side-channel resistant AES architecture utilizing randomized composite field representations.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Area-Efficient FPGA Implementations of the SHA-3 Finalists.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
On FPGA-based implementations of Gröstl.
IACR Cryptol. ePrint Arch., 2010

On FPGA-Based Implementations of the SHA-3 Candidate Grøstl.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

2009
On Optimized FPGA Implementations of the SHA-3 Candidate Groestl.
IACR Cryptol. ePrint Arch., 2009

Selbstorganisierendes Service Level Management basierend auf Mechanismus-Design.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2009


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