Bernhard Eschermann

According to our database, Bernhard Eschermann authored at least 16 papers between 1988 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

Dependability Evaluation of a Computing System for Traction Control of Electrical Locomotives.

Silke Draber, Bernhard Eschermann

Proceedings of the Dependable Computing, 1996

1994

Fail-Safe On-Board Communication for Automatic Train Protection.

Bernhard Eschermann, Hubert D. Kirrmann

Proceedings of the Innovationen bei Rechen- und Kommunikationssystemen, Eine Herausforderung für die Informatik, 24. GI-Jahrestagung im Rahmen des 13th World Computer Congress, IFIP Congress '94, Hamburg, 28. August, 1994

1993

Enhancing on-line testability during synthesis.

Bernhard Eschermann

J. Electron. Test., 1993

State Assignment for Hardwired VLSI Control Units.

Bernhard Eschermann

ACM Comput. Surv., 1993

Funktionaler Entwurf digitaler Schaltungen - Methoden und CAD-Techniken.

Bernhard Eschermann

Springer-Lehrbuch, Springer, ISBN: 978-3-540-56788-2, 1993

1992

Testfreundliche Synthese hochintegrierter Schaltungen

Bernhard Eschermann

PhD thesis, 1992

Optimized synthesis techniques for testable sequential circuits.

Bernhard Eschermann, Hans-Joachim Wunderlich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Synthesis and self-test of random logic control units.

Bernhard Eschermann

Integr., 1992

An implicitly testable boundary scan TAP controller.

Bernhard Eschermann

J. Electron. Test., 1992

On Combining Off-Line BIST and On-Line Control Flow Checking.

Bernhard Eschermann

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Emulation of Scan Paths in Sequential Circuit Synthesis.

Bernhard Eschermann, Hans-Joachim Wunderlich

Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Module Generation for AND/XOR Fields (XPLAs).

Jürgen Frößl, Bernhard Eschermann

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Unified Approach for the Synthesis of Self-Testable Finite State Machines.

Bernhard Eschermann, Hans-Joachim Wunderlich

Proceedings of the 28th Design Automation Conference, 1991

1990

Optimized synthesis of self-testable finite state machines.

Bernhard Eschermann, Hans-Joachim Wunderlich

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1988

PLA based finite state machines using Johnson counters as state memories.

Rainer Amann, Bernhard Eschermann, Utz G. Baitinger

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Hierarchical placement for macrocells: a 'meet in the middle' approach.

Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988