Bernd Koenemann

According to our database, Bernd Koenemann authored at least 10 papers between 1996 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.

David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Test In the Era of "What You see Is NOT What You Get".

Bernd Koenemann

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Design/process learning from electrical test.

Bernd Koenemann

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data.

Bernd Koenemann

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?

Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue.

Bill Bottoms, Jim Chung, Bernd Koenemann, Glenn Shirley, Lisa Spainhower

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

EDA in IBM: past, present, and future.

John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1997

ATE for VLSI: What Challenges Lie Ahead?

D. Cheung, Bernd Koenemann, S. Nishtala, B. West, D. Wu

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996

BIST: Advantages or Limitations?

Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Design Validation: Formal Verification vs. Simulation vs. Functional Testing.

Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996