Bernd Becker
Orcid: 0000-0003-4031-3258Affiliations:
- University of Freiburg, Germany
According to our database1,
Bernd Becker
authored at least 436 papers
between 1982 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2008, "For contributions to the development of algorithms and data structures for testing and verification of integrated circuits".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on zbmath.org
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on orcid.org
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on id.loc.gov
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on d-nb.info
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on isni.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration -.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
2023
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Everything You Always Wanted to Know About Generalization of Proof Obligations in PDR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.
Proceedings of the IEEE European Test Symposium, 2023
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
IEEE Trans. Autom. Control., 2021
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2021
Proceedings of the Sustainable Energy for Smart Cities, 2021
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the e-Energy '21: The Twelfth ACM International Conference on Future Energy Systems, Virtual Event, Torino, Italy, 28 June, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor.
Proceedings of the 30th IEEE Asian Test Symposium, 2021
2020
Proceedings of the NILM '20, 2020
Proceedings of the BuildSys '20: The 7th ACM International Conference on Systems for Energy-Efficient Buildings, 2020
Proceedings of the NASA Formal Methods - 12th International Symposium, 2020
Proceedings of the IEEE European Test Symposium, 2020
2019
J. Satisf. Boolean Model. Comput., 2019
Proceedings of the Fifth International Workshop on Symbolic-Numeric methods for Reasoning about CPS and IoT, 2019
A Versatile High Frequency Electricity Monitoring Framework for Our Future Connected Home.
Proceedings of the Sustainable Energy for Smart Cities, 2019
Proceedings of the IEEE International Test Conference, 2019
Counterexample-Guided Strategy Improvement for POMDPs Using Recurrent Neural Networks.
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019
Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Semi-Automatic Generation and Labeling of Training Data for Non-intrusive Load Monitoring.
Proceedings of the Tenth ACM International Conference on Future Energy Systems, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
SMILE Goes Gaming: Gamification in a Classroom Response System for Academic Teaching.
Proceedings of the 11th International Conference on Computer Supported Education, 2019
Proceedings of the Human Activity Sensing - Corpus and Applications, 2019
2018
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient generation of parametric test conditions for AMS chips with an interval constraint solver.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the Thirty-Fourth Conference on Uncertainty in Artificial Intelligence, 2018
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2018, 2018
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Towards the Fusion of Intrusive and Non-intrusive Load Monitoring: A Hybrid Approach.
Proceedings of the Ninth International Conference on Future Energy Systems, 2018
Characterization of possibly detected faults by accurately computing their detection probability.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Advanced Logic Synthesis, 2018
2017
J. Electron. Test., 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2017 - 20th International Conference, Melbourne, VIC, Australia, August 28, 2017
Proceedings of the Mathematical Aspects of Computer and Information Sciences, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 56th IEEE Annual Conference on Decision and Control, 2017
Proceedings of the ARCADE 2017, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Multi Scale Comput. Syst., 2016
IEEE Trans. Computers, 2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 1st Workshop on Satisfiability Checking and Symbolic Computation co-located with 18th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2016), 2016
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016
PackSens: A Condition and Transport Monitoring System Based on an Embedded Sensor Platform.
Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016
SC<sup>2</sup>: Satisfiability Checking Meets Symbolic Computation - (Project Paper).
Proceedings of the Intelligent Computer Mathematics - 9th International Conference, 2016
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the Hardware and Software: Verification and Testing, 2016
Proceedings of the Hardware and Software: Verification and Testing, 2016
Proceedings of the Technology and Intimacy: Choice or Coercion, 2016
Proceedings of the 46. Jahrestagung der Gesellschaft für Informatik, 2016
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016
Proceedings of the Automated Technology for Verification and Analysis, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Reliab., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Log. Methods Comput. Sci., 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015
Towards Verification of Artificial Neural Networks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015
Proceedings of the FM 2015: Formal Methods, 2015
Improving test pattern generation in presence of unknown values beyond restricted symbolic logic.
Proceedings of the 20th IEEE European Test Symposium, 2015
Identification of high power consuming areas with gate type and logic level information.
Proceedings of the 20th IEEE European Test Symposium, 2015
Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Theor. Comput. Sci., 2014
Sci. Comput. Program., 2014
Proceedings of the Proceedings Twelfth International Workshop on Quantitative Aspects of Programming Languages and Systems, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the Formal Methods for Executable Software Models, 2014
Proceedings of the Quantitative Evaluation of Systems - 11th International Conference, 2014
Implication Graph Compression inside the SMT Solver iSAT3.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Test pattern generation in presence of unknown values based on restricted symbolic logic.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the Hardware and Software: Verification and Testing, 2014
Proceedings of the Formal Methods in Computer-Aided Design, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Mobile Learning mit kontextbezogenen mobilen Diensten in der "KMU Smart Factory": Szenarien und Lösungsansätze für Fertigungsprozesse.
Proceedings of DeLFI Workshops 2014 co-located with 12th e-Learning Conference of the German Computer Society (DeLFI 2014), 2014
An effective approach to automatic functional processor test generation for small-delay faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Automated Technology for Verification and Analysis, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Inf. Secur. J. A Glob. Perspect., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Recent Improvements in the SMT Solver iSAT.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Equivalence Checking for Partial Implementations Revisited.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Stochastic Bounded Model Checking: Bounded Rewards and Compositionality.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2013
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Equivalence checking of partial designs using dependency quantified Boolean formulae.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition.
Proceedings of the Automated Deduction - CADE-24, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
CoRR, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012
Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation).
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012
Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
Enhanced Integration of QBF Solving Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the International SoC Design Conference, 2012
SMILE - Smartphones in A University Learning Environment: A Classroom Response System.
Proceedings of the Future of Learning: Proceedings of the 10th International Conference of the Learning Sciences, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the Formal Aspects of Component Software, 9th International Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
SMILE - Smartphones in Lectures - Initiating a Smartphone-based Audience Response System as a Student Project.
Proceedings of the CSEDU 2012, 2012
Proceedings of the Automated Technology for Verification and Analysis, 2012
Proceedings of the Automated Technology for Verification and Analysis, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IEEE Trans. Dependable Secur. Comput., 2011
Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011
Verifying Incomplete Networks of Timed Automata.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
SMT-based Counterexample Generation for Markov Chains.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the Formal Techniques for Distributed Systems, 2011
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Combinatorial Optimization and Applications, 2011
Proceedings of the Automated Technology for Verification and Analysis, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011
2010
Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).
it Inf. Technol., 2010
Int. J. Parallel Program., 2010
Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs.
Proceedings of the Theory and Applications of Satisfiability Testing, 2010
Proceedings of the QEST 2010, 2010
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the Measurement, 2010
SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Exploiting Different Strategies for the Parallelization of an SMT Solver.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
Proceedings of the Verification over discrete-continuous boundaries, 04.07. - 09.07.2010, 2010
2009
IEEE Trans. Software Eng., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
J. Satisf. Boolean Model. Comput., 2009
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking.
Proceedings of the Verification, 2009
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Stabilization, 2009
Proceedings of the Theory and Applications of Satisfiability Testing, 2009
Picoso - A Parallel Interval Constraint Solver.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009
QmiraXT - A Multithreaded QBF Solver.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 2009 International Conference on High Performance Computing & Simulation, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the 16th RCRA workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion, 2009
2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
The Demand for Reliability in Probabilistic Verification.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Proceedings of the 2008 IEEE International Test Conference, 2008
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Technische Informatik - eine einführende Darstellung.
Oldenbourg, ISBN: 978-3-486-58650-3, 2008
2007
SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme).
it Inf. Technol., 2007
CoRR, 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
AVACS -- Automatic Verification and Analysis of Complex Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Computation of minimal counterexamples by using black box techniques and symbolic methods.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Computer Aided Systems Theory, 2007
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the Computer Aided Verification, 19th International Conference, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
J. Graph Algorithms Appl., 2006
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it Inf. Technol., 2006
J. Electron. Test., 2006
Proceedings of the Fourth International Workshop on Bounded Model Checking, 2006
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006
Proceedings of the Third International Conference on the Quantitative Evaluation of Systems (QEST 2006), 2006
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
Memory-aware Bounded Model Checking for Linear Hybrid Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Automated Technology for Verification and Analysis, 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the Experimental and Efficient Algorithms, 4th InternationalWorkshop, 2005
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Verification, 2005
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005
Knowledge Sharing in a Microcontroller based Parallel SAT Solver.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, 2005
Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface.
Proceedings of the Workshop Proceedings DeLFI 2005 und GMW05, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Technische Informatik - eine Einführung.
Pearson Studium, Pearson Education, ISBN: 978-3-8273-7092-1, 2005
2004
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the SAT 2004, 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Early Conflict Detection Based SAT Solving.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Placement and routing optimization for circuits derived from BDDs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004
2003
Integr., 2003
J. Electron. Test., 2003
Reducing ATE Cost in System-on-Chip Test.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Cross Reduction for Orthogonal Circuit Visualization.
Proceedings of the International Conference on VLSI, 2003
Proceedings of the Theory and Applications of Satisfiability Testing, 2003
The Case for 2-POF.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Conflict-based Selection of Branching Rules in SAT-Algorithms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Proceedings of the 2003 Design, 2003
2002
On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division.
Formal Methods Syst. Des., 2002
Equivalence Checking in the Presence of Incompletely Specified Boxes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002
Symbolic Simulation of Algorithms Specified in HDL.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the Graph Drawing, 10th International Symposium, 2002
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
J. Electron. Test., 2001
Don't Care Minimization of BMDs: Complexity and Algorithms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Supervised Dynamic Recording in Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the Computational Intelligence, 2001
Proceedings of the Evolutionary Multi-Criterion Optimization, 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
The multiple variable order problem for binary decision diagrams: theory and practical application.
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Integr., 2000
State Traversal guided by Hamming Distance Profiles.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Proceedings of the 2000 International Symposium on Physical Design, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Specialized Hardware for Implementation of Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000
Proceedings of the Graph Drawing, 8th International Symposium, 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
J. Electron. Test., 1999
Grouping Heuristics for Word-Level Decision Diagrams.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the Computational Intelligence, 1999
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.
Proceedings of the Digest of Papers: FTCS-29, 1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Computers, 1998
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen.
Leitfäden der Informatik, Teubner, ISBN: 978-3-519-02149-0, 1998
Springer, ISBN: 978-0-7923-8193-8, 1998
1997
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Computers, 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the Parallel Problem Solving from Nature, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the conference on European design automation, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Int. J. Artif. Intell. Tools, 1995
On the application of local circuit transformations with special emphasis on path delay fault testability.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the LATIN '95: Theoretical Informatics, 1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the Artificial Neural Nets and Genetic Algorithms, 1995
Proceedings of the Automata, Languages and Programming, 22nd International Colloquium, 1995
OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation.
Proceedings of the Digest of Papers: FTCS-25, 1995
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
On the implementation of an efficient performance driven generator for conditional-sum-adders.
Proceedings of the European Design Automation Conference 1993, 1993
1992
Proceedings of the STACS 92, 1992
Proceedings of the Mathematical Foundations of Computer Science 1992, 1992
Proceedings of the conference on European design automation, 1992
Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up.
Proceedings of the conference on European design automation, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the Informatik, Festschrift zum 60. Geburtstag von Günter Hotz, 1992
1991
Theor. Comput. Sci., 1991
A uniform test approach for RCC-adders.
Fundam. Informaticae, 1991
Structure based methods for parallel pattern fault simulation in combinational circuits.
Proceedings of the conference on European design automation, 1991
1990
Optimal-Time Multipliers and C-Testability.
J. Inf. Process. Cybern., 1990
Proceedings of the European Design Automation Conference, 1990
1988
Proceedings of the STACS 88, 1988
Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988
1987
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987
1986
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform. Forsch. Entwickl., 1986
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform. Forsch. Entwickl., 1986
Proceedings of the Mathematical Foundations of Computer Science 1986, 1986
Proceedings of the 27th Annual Symposium on Foundations of Computer Science, 1986
1983
Proceedings of the Theoretical Computer Science, 1983
1982
Über die kreuzungsfreie, rechtwinklige Einbettung von gewichteten Graphen in die Ebene.
PhD thesis, 1982