Bernd Becker

Martin Kreuzer

Proceedings of the Mathematical Aspects of Computer and Information Sciences, 2017

Evaluating the effectiveness of D-chains in SAT-based ATPG.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Towards mixed structural-functional models for algebraic fault attacks on ciphers.

[BibT_eX]

[DOI]

Ange-Salomé Messeng Ekossono

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

AutoFault: Towards Automatic Construction of Algebraic Fault Attacks.

[BibT_eX]

[DOI]

Ange-Salomé Messeng Ekossono

Mael Gay

Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017

Specification and verification of security in reconfigurable scan networks.

[BibT_eX]

[DOI]

Laura Rodríguez Gómez

Pascal Raiola

Proceedings of the 22nd IEEE European Test Symposium, 2017

Best paper.

[BibT_eX]

[DOI]

Adit D. Singh

Proceedings of the 22nd IEEE European Test Symposium, 2017

Sensitized path PUF: A lightweight embedded physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Motion planning under partial observability using game-based abstraction.

[BibT_eX]

[DOI]

Proceedings of the 56th IEEE Annual Conference on Decision and Control, 2017

SC-square: when Satisfiability Checking and Symbolic Computation join forces.

[BibT_eX]

[DOI]

Proceedings of the ARCADE 2017, 2017

2016

A Flexible Framework for the Automatic Generation of SBST Programs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

On Metrics to Quantify the Inter-Device Uniqueness of PUFs.

[BibT_eX]

[DOI]

Linus Feiten

IACR Cryptol. ePrint Arch., 2016

Satisfiability Checking meets Symbolic Computation (Project Paper).

[BibT_eX]

[DOI]

CoRR, 2016

Satisfiability checking and symbolic computation.

[BibT_eX]

[DOI]

ACM Commun. Comput. Algebra, 2016

Effective generation and evaluation of diagnostic SBST programs.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Satisfiability Checking and Symbolic Computation co-located with 18th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2016), 2016

iHouse: A Voice-Controlled, Centralized, Retrospective Smart Home.

[BibT_eX]

[DOI]

Benjamin Völker

Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

PackSens: A Condition and Transport Monitoring System Based on an Embedded Sensor Platform.

[BibT_eX]

[DOI]

Marc Pfeifer

Proceedings of the Sensor Systems and Software - 7th International Conference, S-Cube 2016, 2016

Dependency Schemes for DQBF.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

SC2: Satisfiability Checking Meets Symbolic Computation - (Project Paper).

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 9th International Conference, 2016

Applying Tailored Formal Methods to X-ATPG.

[BibT_eX]

[DOI]

Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Known unknowns - Knowledge in the presence of unknowns.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

SAT-Based Combinational and Sequential Dependency Computation.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2016

Advancing Software Model Checking Beyond Linear Arithmetic Theories.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2016

Revocable Anonymisation in Video Surveillance: A "Digital Cloak of Invisibility".

[BibT_eX]

[DOI]

Proceedings of the Technology and Intimacy: Choice or Coercion, 2016

Digitale Tarnkappe: Anonymisierung in Videoaufnahmen.

[BibT_eX]

[DOI]

Proceedings of the 46. Jahrestagung der Gesellschaft für Informatik, 2016

Accurate ICP-based floating-point reasoning.

[BibT_eX]

[DOI]

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Formal verification of secure reconfigurable scan network infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed Parallel #SAT Solving.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

Skolem Functions for DQBF.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2016

On Optimal Power-Aware Path Sensitization.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Transient Reward Approximation for Continuous-Time Markov Chains.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2015

Formal Vulnerability Analysis of Security Components.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

High-level Counterexamples for Probabilistic Automata

[BibT_eX]

[DOI]

Log. Methods Comput. Sci., 2015

Verification of partial designs using incremental QBF.

[BibT_eX]

[DOI]

Paolo Marin

Luis María Ferrer Fioriti

AI Commun., 2015

Improving diagnosis resolution of a fault detection test set.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Abstraction-Based Computation of Reward Measures for Markov Automata.

[BibT_eX]

[DOI]

Bettina Braitling

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

Modeling Unknown Values in Test and Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Preprocessing for DQBF.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015

Laissez-Faire Caching for Parallel #SAT Solving.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015

Towards Verification of Artificial Neural Networks.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Counterexamples for Expected Rewards.

[BibT_eX]

[DOI]

Proceedings of the FM 2015: Formal Methods, 2015

Improving test pattern generation in presence of unknown values beyond restricted symbolic logic.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Identification of high power consuming areas with gate type and logic level information.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

On the automatic generation of SBST test programs for in-field test.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Solving DQBF through quantifier elimination.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Exact Logic and Fault Simulation in Presence of Unknowns.

[BibT_eX]

[DOI]

Luis María Ferrer Fioriti

ACM Trans. Design Autom. Electr. Syst., 2014

Minimal counterexamples for linear-time probabilistic verification.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2014

Symbolic counterexample generation for large discrete-time Markov chains.

[BibT_eX]

[DOI]

Sci. Comput. Program., 2014

QBF with Soft Variables.

[BibT_eX]

[DOI]

Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2014

MeGARA: Menu-based Game Abstraction and Abstraction Refinement of Markov Automata.

[BibT_eX]

[DOI]

Bettina Braitling

Proceedings of the Proceedings Twelfth International Workshop on Quantitative Aspects of Programming Languages and Systems, 2014

Efficient SAT-Based Circuit Initialization for Larger Designs.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

SAT-Based Test Pattern Generation with Improved Dynamic Compaction.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Counterexample Generation for Discrete-Time Markov Models: An Introductory Survey.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Executable Software Models, 2014

Accelerating Parametric Probabilistic Verification.

[BibT_eX]

[DOI]

Proceedings of the Quantitative Evaluation of Systems - 11th International Conference, 2014

Implication Graph Compression inside the SMT Solver iSAT3.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Test pattern generation in presence of unknown values based on restricted symbolic logic.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2014

Using interval constraint propagation for pseudo-Boolean constraint solving.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2014

Variation-aware deterministic ATPG.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Mobile Learning mit kontextbezogenen mobilen Diensten in der "KMU Smart Factory": Szenarien und Lösungsansätze für Fertigungsprozesse.

[BibT_eX]

[DOI]

Proceedings of DeLFI Workshops 2014 co-located with 12th e-Learning Conference of the German Computer Society (DeLFI 2014), 2014

An effective approach to automatic functional processor test generation for small-delay faults.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Using MaxBMC for Pareto-optimal circuit initialization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Efficient SMT-based ATPG for interconnect open defects.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Incremental Encoding and Solving of Cardinality Constraints.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2014

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs.

[BibT_eX]

[DOI]

Inf. Secur. J. A Glob. Perspect., 2013

SAT-Based Analysis of Sensitizable Paths.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Identification of critical variables using an FPGA-based fault injection framework.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Proving QBF-hardness in Bounded Model Checking for Incomplete Designs.

[BibT_eX]

[DOI]

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Recent Improvements in the SMT Solver iSAT.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Equivalence Checking for Partial Implementations Revisited.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Stochastic Bounded Model Checking: Bounded Rewards and Compositionality.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Accurate Computation of Sensitizable Paths Using Answer Set Programming.

[BibT_eX]

[DOI]

Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

Early-life-failure detection using SAT-based ATPG.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Equivalence checking of partial designs using dependency quantified Boolean formulae.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

SMILE: Smartphones in der Lehre - ein Rück- und Überblick.

[BibT_eX]

[DOI]

Linus Feiten

Katrin Weber

Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Accurate QBF-based test pattern generation in presence of unknown values.

[BibT_eX]

[DOI]

Stefan Hillebrecht

Proceedings of the Design, Automation and Test in Europe, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition.

[BibT_eX]

[DOI]

Proceedings of the Automated Deduction - CADE-24, 2013

Search Space Reduction for Low-Power Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Accurate Multi-cycle ATPG in Presence of X-Values.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Provably optimal test cube generation using quantified boolean formula solving.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Transient Reward Approximation for Grids, Crowds, and Viruses

[BibT_eX]

[DOI]

CoRR, 2012

The COMICS Tool - Computing Minimal Counterexamples for Discrete-time Markov Chains

[BibT_eX]

[DOI]

CoRR, 2012

SAT-ATPG using preferences for improved detection of complex defect mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Minimal Critical Subsystems for Discrete-Time Markov Models.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation).

[BibT_eX]

[DOI]

Paolo Marin

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Enhanced Integration of QBF Solving Techniques.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Functional test of small-delay faults using SAT and Craig interpolation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

TSV and DFT cost aware circuit partitioning for 3D-SOCs.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Performance aware partitioning for 3D-SOCs.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

SMILE - Smartphones in A University Learning Environment: A Classroom Response System.

[BibT_eX]

[DOI]

Proceedings of the Future of Learning: Proceedings of the 10th International Conference of the Learning Sciences, 2012

Small-delay-fault ATPG with waveform accuracy.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Symbolic Counterexample Generation for Discrete-Time Markov Chains.

[BibT_eX]

[DOI]

Proceedings of the Formal Aspects of Component Software, 9th International Symposium, 2012

On the quality of test vectors for post-silicon characterization.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Exact stuck-at fault classification in presence of unknowns.

[BibT_eX]

[DOI]

Stefan Hillebrecht

Proceedings of the 17th IEEE European Test Symposium, 2012

Multi-conditional SAT-ATPG for power-droop testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

#SAT-based vulnerability analysis of security components - A case study.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Verification of partial designs using incremental QBF solving.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

On the optimality of K longest path generation algorithm under memory constraints.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SMILE - Smartphones in Lectures - Initiating a Smartphone-based Audience Response System as a Student Project.

[BibT_eX]

Proceedings of the CSEDU 2012, 2012

The COMICS Tool - Computing Minimal Counterexamples for DTMCs.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2012

ALLQBF Solving by Computational Learning.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2012

Variation-Aware Fault Grading.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Modeling and Mitigating Transient Errors in Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2011

Parallel SAT Solving in Bounded Model Checking.

[BibT_eX]

[DOI]

J. Log. Comput., 2011

Parallel QBF Solving with Advanced Knowledge Sharing.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2011

Incremental preprocessing methods for use in BMC.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2011

Variation-aware fault modeling.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2011

Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.

[BibT_eX]

[DOI]

Karina Gitina

Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

Reachability analysis for incomplete networks of Markov decision processes.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Verifying Incomplete Networks of Timed Automata.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

SMT-based Counterexample Generation for Markov Chains.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Estimation of component criticality in early design steps.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Counterexample Generation for Markov Chains Using SMT-Based Bounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques for Distributed Systems, 2011

Craig Interpolation in the Presence of Non-linear Constraints.

[BibT_eX]

[DOI]

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2011

Towards Variation-Aware Test Methods.

[BibT_eX]

[DOI]

Sybille Hellebrand

Peter C. Maxwell

Proceedings of the 16th European Test Symposium, 2011

SAT-based analysis of sensitisable paths.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Proof certificates and non-linear arithmetic constraints.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Integration of orthogonal QBF solving techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Integration of an LP Solver into Interval Constraint Propagation.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Optimization and Applications, 2011

Hierarchical Counterexamples for Discrete-Time Markov Chains.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2011

Efficient SAT-Based Search for Longest Sensitisable Paths.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Fault diagnosis aware ATE assisted test response compaction.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Bounded Fairness for Probabilistic Distributed Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010

Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).

[BibT_eX]

[DOI]

it Inf. Technol., 2010

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2010

Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems.

[BibT_eX]

[DOI]

Proceedings of the QEST 2010, 2010

DTMC Model Checking by SCC Reduction.

[BibT_eX]

[DOI]

Proceedings of the QEST 2010, 2010

Bounded Model Checking of Incomplete Networks of Timed Automata.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Correctness Issues of Symbolic Bisimulation Computation for Markov Chains.

[BibT_eX]

[DOI]

Proceedings of the Measurement, 2010

SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Exploiting Different Strategies for the Parallelization of an SMT Solver.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

10271 Abstracts Collection - Verification over discrete-continuous boundaries.

[BibT_eX]

[DOI]

Proceedings of the Verification over discrete-continuous boundaries, 04.07. - 09.07.2010, 2010

2009

Compositional Dependability Evaluation for STATEMATE.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 2009

SUPERB: Simulator utilizing parallel evaluation of resistive bridges.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

PaMiraXT: Parallel SAT Solving with Threads and Message Passing.

[BibT_eX]

[DOI]

Matthew Lewis

J. Satisf. Boolean Model. Comput., 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking.

[BibT_eX]

[DOI]

Bettina Braitling

Proceedings of the Verification, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Dependability Engineering of Silent Self-stabilizing Systems.

[BibT_eX]

[DOI]

Proceedings of the Stabilization, 2009

PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2009

Picoso - A Parallel Interval Constraint Solver.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

QmiraXT - A Multithreaded QBF Solver.

[BibT_eX]

Matthew Lewis

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

ATPG-based grading of strong fault-secureness.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Comparison of knowledge sharing strategies in a parallel QBF solver.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on High Performance Computing & Simulation, 2009

Reducing temperature variability by routing heat pipes.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Dynamic Compaction in SAT-Based ATPG.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Evaluation of Knowledge Sharing Strategies in a Parallel QBF Solver.

[BibT_eX]

[DOI]

Proceedings of the 16th RCRA workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion, 2009

2008

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Automatic Test Pattern Generation for Interconnect Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

The Demand for Reliability in Probabilistic Verification.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.

[BibT_eX]

[DOI]

Sudhakar M. Reddy

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Propositional approximations for bounded model checking of partial circuit designs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Selective Hardening in Early Design Steps.

[BibT_eX]

[DOI]

Christian G. Zoellin

Proceedings of the 13th European Test Symposium, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

A study of cognitive resilience in a JPEG compressor.

[BibT_eX]

[DOI]

Damian Nowroth

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

On Reducing Circuit Malfunctions Caused by Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Probabilistic Model Checking and Reliability of Results.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Resistive Bridging Fault Simulation of Industrial Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Technische Informatik - eine einführende Darstellung.

[BibT_eX]

Oldenbourg, ISBN: 978-3-486-58650-3, 2008

2007

SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme).

[BibT_eX]

[DOI]

Ernst-Rüdiger Olderog

Reinhard Wilhelm

it Inf. Technol., 2007

Power Droop Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors

[BibT_eX]

[DOI]

Stefan Spinner

Julian Bartholomeyczik

CoRR, 2007

An Analysis Framework for Transient-Error Tolerance.

[BibT_eX]

[DOI]

John P. Hayes

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Application of Lifting in Partial Design Analysis.

[BibT_eX]

[DOI]

Vanessa Struve

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

AVACS -- Automatic Verification and Analysis of Complex Systems.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Identification of Critical Errors in Imaging Applications.

[BibT_eX]

[DOI]

Damian Nowroth

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Computation of minimal counterexamples by using black box techniques and symbolic methods.

[BibT_eX]

[DOI]

Tobias Nopper

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimization techniques for BDD-based bisimulation computation.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

On Combining 01X-Logic and QBF.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Systems Theory, 2007

On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

Simulating Open-Via Defects.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Multithreaded SAT Solving.

[BibT_eX]

[DOI]

Matthew Lewis

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

X-masking during logic BIST and its impact on defect coverage.

[BibT_eX]

[DOI]

Yuyi Tang

IEEE Trans. Very Large Scale Integr. Syst., 2006

Simulating Resistive-Bridging and Stuck-At Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Orthogonal Hypergraph Drawing for Improved Visibility.

[BibT_eX]

[DOI]

J. Graph Algorithms Appl., 2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).

[BibT_eX]

[DOI]

it Inf. Technol., 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

Bounded Model Checking with Parametric Data Structures.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Bounded Model Checking, 2006

A Definition and Classification of Timing Anomalies.

[BibT_eX]

[DOI]

Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Compositional Performability Evaluation for STATEMATE.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on the Quantitative Evaluation of Systems (QEST 2006), 2006

Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Memory-aware Bounded Model Checking for Linear Hybrid Systems.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Low-Cost Hardening of Image Processing Applications Against Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Minimization of Large State Spaces using Symbolic Branching Bisimulation.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Sigref- A Symbolic Bisimulation Tool Box.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2006

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Delta-IDDQ Testing of Resistive Short Defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Modeling Feedback Bridging Faults with Non-Zero Resistance.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

BDDs in a Branch and Cut Framework.

[BibT_eX]

[DOI]

Proceedings of the Experimental and Efficient Algorithms, 4th InternationalWorkshop, 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Optimizing Bounded Model Checking for Linear Hybrid Systems.

[BibT_eX]

[DOI]

Proceedings of the Verification, 2005

Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Speedup Techniques Utilized in Modern SAT Solvers.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Securing Wireless Networks in a University Environment.

[BibT_eX]

[DOI]

Jochen Eisinger

Peter Winterer

Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

Knowledge Sharing in a Microcontroller based Parallel SAT Solver.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

PaMira - A Parallel SAT Solver with Knowledge Sharing.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

On SAT-based Bounded Invariant Checking of Blackbox Designs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Transient fault characterization in dynamic noisy environments.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Lemma Exchange in a Microcontroller Based Parallel SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A unified fault model and test generation procedure for interconnect opens and bridges.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface.

[BibT_eX]

[DOI]

Martina Welte

Proceedings of the Workshop Proceedings DeLFI 2005 und GMW05, 2005

Evolutionary Optimization in Code-Based Test Compression.

[BibT_eX]

[DOI]

Alejandro Czutro

Proceedings of the 2005 Design, 2005

A Family of Logical Fault Models for Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Technische Informatik - eine Einführung.

[BibT_eX]

Pearson Studium, Pearson Education, ISBN: 978-3-8273-7092-1, 2005

2004

Scalable Delay Fault BIST for Use with Low-Cost ATE.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Early Conflict Detection Based BCP for SAT Solving.

[BibT_eX]

[DOI]

Proceedings of the SAT 2004, 2004

PICHAFF2 - A Hierarchical Parallel SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.

[BibT_eX]

[DOI]

Thomas Kmieciak

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Early Conflict Detection Based SAT Solving.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.

[BibT_eX]

[DOI]

Yuyi Tang

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Placement and routing optimization for circuits derived from BDDs.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Orthogonal hypergraph routing for improved visibility.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Testing for Missing-Gate Faults in Reversible Circuits.

[BibT_eX]

[DOI]

John P. Hayes

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Distributed SAT Solver for Microcontroller.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2004, 2004

Parallel SAT Solving with Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004

2003

Exact Routing with Search Space Reduction.

[BibT_eX]

[DOI]

Frank Schmiedle

IEEE Trans. Computers, 2003

Pattern-based verification of connections to intellectual property cores.

[BibT_eX]

[DOI]

Integr., 2003

Polynomial Formal Verification of Multipliers.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

Multiple Scan Chain Design for Two-Pattern Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Reducing ATE Cost in System-on-Chip Test.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

Cross Reduction for Orthogonal Circuit Visualization.

[BibT_eX]

Proceedings of the International Conference on VLSI, 2003

Conflict-Based Selection of Branching Rules.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2003

The Case for 2-POF.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Conflict-based Selection of Branching Rules in SAT-Algorithms.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.

[BibT_eX]

[DOI]

Sudhakar M. Reddy

Proceedings of the 2003 Design, 2003

2002

On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division.

[BibT_eX]

[DOI]

Thomas M. Weis

Formal Methods Syst. Des., 2002

Equivalence Checking in the Presence of Incompletely Specified Boxes.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Symbolic Simulation of Algorithms Specified in HDL.

[BibT_eX]

Klaus-Jürgen Englert

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.

[BibT_eX]

[DOI]

Piet Engelke

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Sequential n -Detection Criteria: Keep It Simple.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Stop & Go BIST.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Checking Equivalence for Circuits Containing Incompletely Specified Boxes.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Crossing Reduction by Windows Optimization.

[BibT_eX]

[DOI]

Proceedings of the Graph Drawing, 10th International Symposium, 2002

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.

[BibT_eX]

[DOI]

Irith Pomeranz

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

Don't Care Minimization of BMDs: Complexity and Algorithms.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Supervised Dynamic Recording in Model Checking.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Exploiting don't cares to minimize *BMDs.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence, 2001

Multi-objective Optimisation Based on Relation Favour.

[BibT_eX]

[DOI]

Proceedings of the Evolutionary Multi-Criterion Optimization, 2001

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Checking Equivalence for Partial Implementations.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Efficient Pattern-Based Verification of Connections to IP Cores .

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

The multiple variable order problem for binary decision diagrams: theory and practical application.

[BibT_eX]

[DOI]

Andreas Brogle

Proceedings of ASP-DAC 2001, 2001

Application of linearly transformed BDDs in sequential verification.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

OKFDD minimization by genetic algorithms with application to circuit design.

[BibT_eX]

[DOI]

Integr., 2000

State Traversal guided by Hamming Distance Profiles.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Exact switchbox routing with search space reduction.

[BibT_eX]

[DOI]

Frank Schmiedle

Daniel Unruh

Proceedings of the 2000 International Symposium on Physical Design, 2000

Minimization of Ordered Pseudo Kronecker Decision Diagrams.

[BibT_eX]

[DOI]

Per Lindgren

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Specialized Hardware for Implementation of Evolutionary Algorithms.

[BibT_eX]

Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

k-Layer Straightline Crossing Minimization by Speeding Up Sifting.

[BibT_eX]

[DOI]

Proceedings of the Graph Drawing, 8th International Symposium, 2000

Verification of Designs Containing Black Boxes.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Testability of Circuits Derived from Lattice Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

A parameterizable fault simulator for bridging faults.

[BibT_eX]

[DOI]

Piet Engelke

Proceedings of the 5th European Test Workshop, 2000

On the Generation of Multiplexer Circuits for Pass Transistor Logic.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Distance driven finite state machine traversal.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Testability of 2-Level AND/EXOR Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Hybrid Fault Simulation for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Grouping Heuristics for Word-Level Decision Diagrams.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Exact channel routing using symbolic representation.

[BibT_eX]

[DOI]

Frank Schmiedle

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Synthesis of Pseudo Kronecker Lattice Diagrams.

[BibT_eX]

[DOI]

Per Lindgren

Proceedings of the IEEE International Conference On Computer Design, 1999

Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence, 1999

Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-29, 1999

A scalable BIST architecture for delay faults.

[BibT_eX]

[DOI]

Proceedings of the 4th European Test Workshop, 1999

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

On Variable Ordering and Decomposition Type Choice in OKFDDs.

[BibT_eX]

[DOI]

Andrea Jahnke

IEEE Trans. Computers, 1998

Testing with decision diagrams.

[BibT_eX]

[DOI]

Integr., 1998

Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.

[BibT_eX]

[DOI]

Per Lindgren

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Word-level decision diagrams, WLCDs and division.

[BibT_eX]

[DOI]

Thomas M. Weis

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen.

[BibT_eX]

Leitfäden der Informatik, Teubner, ISBN: 978-3-519-02149-0, 1998

Binary Decision Diagrams - Theory and Implementation.

[BibT_eX]

[DOI]

Springer, ISBN: 978-0-7923-8193-8, 1998

1997

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On the Expressive Power of OKFDDs.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1997

The K*BMD: A Verification Data Structure.

[BibT_eX]

[DOI]

Stefan Ruppertz

IEEE Des. Test Comput., 1997

On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

(Quasi-) Linear Path Delay Fault Tests for Adders.

[BibT_eX]

[DOI]

Sudhakar M. Reddy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Manipulation Algorithms for K*BMDs.

[BibT_eX]

[DOI]

Stefan Ruppertz

Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1997

Fault Simulation in Sequential Multi-Valued Logic Networks.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Functional simulation using binary decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast and efficient construction of BDDs by reordering based synthesis.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Learning heuristics for OKFDD minimization by evolutionary algorithms.

[BibT_eX]

[DOI]

Nicole Göckel

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

On the representational power of bit-level and word-level decision diagrams.

[BibT_eX]

[DOI]

Reinhard Enders

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

On the (non-)resetability of synchronous sequential circuits.

[BibT_eX]

[DOI]

Birgitta Stenner

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Learning Heuristics for OBDD Minimization by Evolutionary Algorithms.

[BibT_eX]

[DOI]

Nicole Göckel

Proceedings of the Parallel Problem Solving from Nature, 1996

Local Transformations and Robust Dependent Path Delay.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

MORE: an alternative implementation of BDD packages by multi-operand synthesis.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

K*BMDs: A New Data Structure for Verification.

[BibT_eX]

[DOI]

Stefan Ruppertz

Proceedings of the 1996 European Design and Test Conference, 1996

A Fast Optimal Robust Path Delay Fault Testable Adder.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.

[BibT_eX]

[DOI]

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

On the generation of area-time optimal testable adders.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On the testability of iterative logic arrays.

[BibT_eX]

[DOI]

Integr., 1995

A Genetic Algorithm for Decomposition Type Choice in OKFDDs.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 1995

On the Relation between BDDs and FDDs.

[BibT_eX]

[DOI]

Ralph Werchner

Inf. Comput., 1995

On local transformations and path delay fault testability.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

On the application of local circuit transformations with special emphasis on path delay fault testability.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On the Relation Betwen BDDs and FDDs.

[BibT_eX]

[DOI]

Ralph Werchner

Proceedings of the LATIN '95: Theoretical Informatics, 1995

Random Pattern Fault Simulation in Multi-Valued Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Dynamic minimization of OKFDDs.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions.

[BibT_eX]

[DOI]

Nicole Göckel

Proceedings of the Artificial Neural Nets and Genetic Algorithms, 1995

OKFDDs versus OBDDs and OFDDs.

[BibT_eX]

[DOI]

Proceedings of the Automata, Languages and Programming, 22nd International Colloquium, 1995

OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation.

[BibT_eX]

[DOI]

Can Ökmen

Proceedings of the Digest of Papers: FTCS-25, 1995

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

How many decomposition types do we need? [decision diagrams].

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

Learning heuristics by genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

A Hybrid Fault Simulator for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Hierarchical Approach to Fault Collapsing.

[BibT_eX]

[DOI]

Ralf Hahn

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Fast OFDD based minimization of fixed polarity Reed-Muller expressions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Testability of Circuits Derived from Functional Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

A BDD - based Algorithm for Computation of Exact Fault Detection Probabilities.

[BibT_eX]

[DOI]

R. Sinkovic

Proceedings of the Digest of Papers: FTCS-23, 1993

On the implementation of an efficient performance driven generator for conditional-sum-adders.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

1992

Synthesis for Testability: Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the STACS 92, 1992

Some Remarks on the Test Complexity of Iterative Logic Arrays.

[BibT_eX]

[DOI]

Joachim Hartmann

Proceedings of the Mathematical Foundations of Computer Science 1992, 1992

A performance driven generator for efficient testable conditional-sum-adders.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up.

[BibT_eX]

[DOI]

Ralf Hahn

Proceedings of the conference on European design automation, 1992

A time optimal robust path-delay-fault self-testable adder.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Synthesis for Testability: Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Informatik, Festschrift zum 60. Geburtstag von Günter Hotz, 1992

1991

Computations over Finite Monoids and their Test Complexity.

[BibT_eX]

[DOI]

Uwe Sparmann

Theor. Comput. Sci., 1991

A uniform test approach for RCC-adders.

[BibT_eX]

Uwe Sparmann

Fundam. Informaticae, 1991

Structure based methods for parallel pattern fault simulation in combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

1990

Optimal-Time Multipliers and C-Testability.

[BibT_eX]

Joachim Hartmann

J. Inf. Process. Cybern., 1990

A graphical system for hierarchical specifications and checkups of VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

1988

How Robust Is The n-Cube?

[BibT_eX]

[DOI]

Hans Ulrich Simon

Inf. Comput., May, 1988

Efficient Testing of Optimal Time Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1988

On the Construction of Optimal Time Adders (Extended Abstract).

[BibT_eX]

[DOI]

Reiner Kolla

Proceedings of the STACS 88, 1988

Regular Structures and Testing: RCC-Adders.

[BibT_eX]

[DOI]

Uwe Sparmann

Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988

1987

Layouts with Wires of Balanced Length

[BibT_eX]

[DOI]

Hans-Georg Osthof

Inf. Comput., April, 1987

On the Optimal Layout of Planar Graphs with Fixed Boundary.

[BibT_eX]

[DOI]

Günter Hotz

SIAM J. Comput., 1987

An Easily Testable Optimal-Time VLSI-Multiplier.

[BibT_eX]

[DOI]

Acta Informatica, 1987

Hierarchical Design Based on a Calculus of Nets.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.

[BibT_eX]

Inform. Forsch. Entwickl., 1986

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.

[BibT_eX]

Inform. Forsch. Entwickl., 1986

Efficient Testing of Optimal Time Adders (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the Mathematical Foundations of Computer Science 1986, 1986

How Robust Is the n-Cube? (Extended Abstract)

[BibT_eX]

[DOI]

Hans Ulrich Simon

Proceedings of the 27th Annual Symposium on Foundations of Computer Science, 1986

1983

On the crossing-free, rectangular embedding of weighted graphs in the plane.

[BibT_eX]

[DOI]

Proceedings of the Theoretical Computer Science, 1983

1982

Über die kreuzungsfreie, rechtwinklige Einbettung von gewichteten Graphen in die Ebene.

[BibT_eX]

[DOI]