Bernard Lepley

According to our database1, Bernard Lepley authored at least 10 papers between 1998 and 2004.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Design of a high speed parallel encoder for convolutional codes.
Microelectron. J., 2004

Designing a High Speed Decoder for Cyclic Codes.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003
A methodology to design a multimedia processor core.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A High Speed Encoder for Recursive Systematic Convolutive Codes.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001
Fast Configurable Polynomial Division for Error Control Coding Applications.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Design of a selective digital filter for a DAVIC compliant modem.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1998
A high-speed parallel DSP architecture dedicated to digital modem applications.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Design of radiofrequency stages for a high rate digital modem.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


  Loading...