Bernard Goossens

According to our database1, Bernard Goossens authored at least 21 papers between 1995 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2021
Deterministic OpenMP and the LBP Parallelizing Manycore Processor.
Proceedings of the Parallel Computing Technologies, 2021

2017
Computing on many cores.
Concurr. Comput. Pract. Exp., 2017

2016
Parallel Locality and Parallelization Quality.
Proceedings of the 7th International Workshop on Programming Models and Applications for Multicores and Manycores, 2016

2015
Toward a Core Design to Distribute an Execution on a Manycore Processor.
Proceedings of the Parallel Computing Technologies - 13th International Conference, PaCT 2015, Petrozavodsk, Russia, August 31, 2015

2013
De quoi est faite une trace d'exécution ?
Tech. Sci. Informatiques, 2013

Limits of Instruction-Level Parallelism Capture.
Proceedings of the International Conference on Computational Science, 2013

2011
Accélération de la simulation modulaire.
Tech. Sci. Informatiques, 2011

2010
PerPI: A Tool to Measure Instruction Level Parallelism.
Proceedings of the Applied Parallel and Scientific Computing, 2010

2009
Heterogeneous Multi-processor SoC Design: Hardware Bridging and Exploration Methodology.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

Software Platform based Embedded Multiprocessor SoC Prototyping.
Proceedings of the 2nd Conférence Internationale sur l'Informatique et ses Applications (CIIA'09), 2009

2006
Ordonnancement distribué d'instructions.
Tech. Sci. Informatiques, 2006

2005
The instruction register file micro-architecture.
Future Gener. Comput. Syst., 2005

2003
The Instruction Register File.
Proceedings of the Parallel Computing Technologies, 2003

2002
Typing the ISA to cluster the processor.
Future Gener. Comput. Syst., 2002

2001
Handling 16 instructions per cycle in a superscalar processor.
Future Gener. Comput. Syst., 2001

1999
Hardware and Software Optimizations for Multimedia Databases.
Proceedings of the Parallel Computing Technologies, 1999

1997
A Multithreaded Vector Co-processor.
Proceedings of the Parallel Computing Technologies, 1997

1996
Les architectures risc et polo: un processeur oriente objet.
Bull. dInformatique Approfondie et Appl., 1996

Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.
Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

On-Chip Multiprocessing.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
Further Pipelining and Multithreading to Improve RISC Processor Speed. A Proposed Architecture and Simulation Results.
Proceedings of the Parallel Computing Technologies, 1995


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