Bernard Dieny

Orcid: 0000-0002-0575-5301

According to our database1, Bernard Dieny authored at least 22 papers between 2007 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to the development of nanomagnetism and spin-electronic devices, including spin valves".

Timeline

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Links

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Bibliography

2024
Roadmap to Neuromorphic Computing with Emerging Technologies.
CoRR, 2024

2023
Microstructured Magnetoelastic Membrane for Magnetic Bioactuators and Soft Artificial Muscles Applications.
Adv. Intell. Syst., September, 2023

2021
PSA-STT-MRAM solution for extended temperature stability.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Spin transfer torque magnetic random-access memory: Towards sub-10 nm devices.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2016
Spintronics [Scanning the Issue].
Proc. IEEE, 2016

Magnetoresistive Random Access Memory.
Proc. IEEE, 2016

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Magnetic memories: From DRAM replacement to ultra low power logic chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Breakdown mechanisms in MgO based magnetic tunnel junctions and correlation with low frequency noise.
Microelectron. Reliab., 2013

Emerging hybrid logic circuits based on non-volatile magnetic memories.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Scalability and logic functionalities of TA-MRAMs.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Non-volatile FPGAs based on spintronic devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011
Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2009

2007
CMOS/Magnetic Hybrid Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

TAS-MRAM based Non-volatile FPGA logic circuit.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007


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