Benoit Nadeau-Dostie

According to our database, Benoit Nadeau-Dostie authored at least 31 papers between 1989 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

Combining Built-In Redundancy Analysis with ECC for Memory Testing.

Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim

Proceedings of the IEEE European Test Symposium, 2024

2023

Transitioning eMRAM from Pilot Project to Volume Production.

Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim

Proceedings of the IEEE International Test Conference, 2023

2022

Configurable BISR Chain For Fast Repair Data Loading.

Wei Zou, Benoit Nadeau-Dostie

Proceedings of the IEEE International Test Conference, 2022

2020

MBIST Supported Multi Step Trim for Reliable eMRAM Sensing.

Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda

Proceedings of the IEEE International Test Conference, 2020

Memory repair logic sharing techniques and their impact on yield.

Benoit Nadeau-Dostie, Luc Romain

Proceedings of the IEEE International Test Conference, 2020

MBIST Support for Reliable eMRAM Sensing.

Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa

Proceedings of the IEEE European Test Symposium, 2020

2018

Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions.

Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

Adapting an industrial memory BIST solution for testing CAMs.

Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim

Proceedings of the International Test Conference in Asia, 2017

2015

Low-Power Programmable PRPG With Test Compression Capabilities.

Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Timing-Aware ATPG.

Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2012

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.

Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie

IEEE Trans. Computers, 2012

Test generator with preselected toggling for low power built-in self-test.

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011

Power Aware Embedded Test.

Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009

Improved Core Isolation and Access for Hierarchical Embedded Test.

Benoit Nadeau-Dostie, Saman Adham, Russell Abbott

IEEE Des. Test Comput., 2009

Test point insertion using functional flip-flops to drive control points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks.

Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote

Proceedings of the 2008 IEEE International Test Conference, 2008

2006

OCI: Open Compression Interface.

Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie

Proceedings of the 2006 IEEE International Test Conference, 2006

2004

A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.

Saman Adham, Benoit Nadeau-Dostie

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2002

Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.

Stephen K. Sunter, Benoit Nadeau-Dostie

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.

Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An embedded technique for at-speed interconnect testing.

Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1996

Built-In Self-Test: Assuring System Integrity.

Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie

Computer, 1996

1995

A New Hardware Fault Insertion Scheme for System Diagnostics Verification.

Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

ScanBist: A Multifrequency Scan-Based BIST Method.

Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan

IEEE Des. Test Comput., 1994

1992

BIST of PCB interconnects using boundary-scan architecture.

Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Scan testing of latch arrays.

Michael M. Y. Hui, Benoit Nadeau-Dostie

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

ScanBIST: A Multi-frequency Scan-based BIST Method.

Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990

Serial Interfacing for Embedded-Memory Testing.

Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal

IEEE Des. Test Comput., 1990

A new procedure for weighted random built-in self-test.

Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

Testing of Glue Logic Interconnects Using Boundary Scan Architecture.

Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie

Proceedings of the Proceedings International Test Conference 1989, 1989