Benoît Dupont de Dinechin
Orcid: 0000-0002-3164-2765
According to our database1,
Benoît Dupont de Dinechin
authored at least 58 papers
between 1991 and 2023.
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Bibliography
2023
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
2022
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
Proceedings of the Next Generation Arithmetic - Third International Conference, 2022
2021
Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities.
IEEE Signal Process. Mag., 2021
Proceedings of the IEEE Statistical Signal Processing Workshop, 2021
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021
2020
Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks.
Perform. Evaluation, 2020
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020
2019
Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip.
Proceedings of the 27th International Conference on Real-Time Networks and Systems, 2019
Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems.
Des. Autom. Embed. Syst., 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors.
Proceedings of the 36th IEEE International Performance Computing and Communications Conference, 2017
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017
Asynchronous one-sided communications and synchronizations for a clustered manycore processor.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
Proceedings of the Euromicro Conference on Digital System Design, 2017
Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources.
Real Time Syst., 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the Parallel Computing: On the Road to Exascale, 2015
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
Converging to periodic schedules for cyclic scheduling problems with resources and deadlines.
Comput. Oper. Res., 2014
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Compiler Construction - 23rd International Conference, 2014
2013
Scheduling an interval ordered precedence graph with communication delays and a limited number of processors.
RAIRO Oper. Res., 2013
A Distributed Run-Time Environment for the Kalray MPPA<sup>®</sup>-256 Integrated Manycore Processor.
Proceedings of the International Conference on Computational Science, 2013
Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor.
Proceedings of the International Conference on Computational Science, 2013
A clustered manycore processor architecture for embedded and accelerated applications.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013
2012
ACM Trans. Archit. Code Optim., 2012
K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
2011
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors.
ACM Trans. Embed. Comput. Syst., 2011
A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs.
Proceedings of the Programming Languages and Systems - 9th Asian Symposium, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2009
Proceedings of the CGO 2009, 2009
2008
Proceedings of the Euro-Par 2008, 2008
Proceedings of the Sixth International Symposium on Code Generation and Optimization (CGO 2008), 2008
2006
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
2005
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2000
Proceedings of the 2000 International Conference on Compilers, 2000
1999
Proceedings of the Compiler Construction, 8th International Conference, 1999
1997
Proceedings of the Parallel Computing Technologies, 1997
Proceedings of the Languages and Compilers for Parallel Computing, 1997
1996
Proceedings of the Languages and Compilers for Parallel Computing, 1996
1995
Proceedings of the Languages and Compilers for Parallel Computing, 1995
1994
Proceedings of the Parallel Architectures and Compilation Techniques, 1994
1992
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992
1991
Proceedings of the Proceedings Supercomputing '91, 1991