Benno Stabernack

Orcid: 0000-0002-6654-1606

Affiliations:
  • Fraunhofer Institute for Telecommunications - Heinrich Hertz Institute (HHI), Berlin, Germany
  • University of Potsdam, Germany


According to our database1, Benno Stabernack authored at least 41 papers between 1999 and 2024.

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Bibliography

2024
An Approach Towards Distributed DNN Training on FPGA Clusters.
Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024

2023
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Challenges Using FPGA Clusters for Distributed CNN Training.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

FPGA-Based Network-Attached Accelerators - An Environmental Life Cycle Perspective.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2022
Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification.
J. Signal Process. Syst., 2022

Towards an optimal right-turn assistant system to avoid accidents with vulnerable traffic participants.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
A Full-Featured FPGA-Based Pipelined Architecture for SIFT Extraction.
IEEE Access, 2021

Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures.
Proceedings of the IEEE International Conference on Smart Cloud, 2020

A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2020

A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Multi-Sensor-Fusion System for People Counting Applications.
Proceedings of the First International Conference on Societal Automation, 2019

Using Time-of-Flight Sensors for People Counting Applications.
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

2018
Modeling the Energy Consumption of the HEVC Decoding Process.
IEEE Trans. Circuits Syst. Video Technol., 2018

2017
Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures.
J. Syst. Archit., 2017

2015
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format.
J. Signal Process. Syst., 2014

Hardware implementation of a full HD real-time disparity estimation algorithm.
IEEE Trans. Consumer Electron., 2014

FPGA implementation of a full HD real-time HEVC main profile decoder.
IEEE Trans. Consumer Electron., 2014

A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC.
Proceedings of the IEEE Fourth International Conference on Consumer Electronics Berlin, 2014

2013
Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing.
IEEE Trans. Circuits Syst. Video Technol., 2013

Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

Architectural decomposition of video decoders for many core architectures.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

2010


2009
Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures.
IEEE Trans. Circuits Syst. Video Technol., 2009

Power Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

2008
Generic algorithms for motion compensation and transformation.
Proceedings of the Real-Time Image Processing 2008, San Jose, CA, USA, January 28-29, 2008, 2008

2007
A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications.
IEEE Trans. Consumer Electron., 2007

Performance and Memory Profiling for Embedded System Design.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2004
Tool-aided performance analysis and optimization of multimedia applications.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

2003
A system for QOS-enabled MPEG-4 video transmission over Bluetooth for mobile applications.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

1999
Instruction Set Extensions for MPEG-4 Video.
J. VLSI Signal Process., 1999


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