Benedikt Noethen

According to our database1, Benedikt Noethen authored at least 15 papers between 2012 and 2018.

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Bibliography

2018
A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

2017

2016
A database accelerator for energy-efficient query processing and optimization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016


M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
Untersuchungen von Kommunikationsmechanismen in heterogenen Mehrprozessorsystemen.
PhD thesis, 2015

Demo abstract: Taming many heterogeneous cores.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Query processing on low-energy many-core processors.
Proceedings of the 31st IEEE International Conference on Data Engineering Workshops, 2015

Towards dependable CPS infrastructures: Architectural and operating-system challenges.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

2014
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs.
ACM Trans. Embed. Comput. Syst., 2014

CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 cores.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Towards elastic SDR architectures using dynamic task management.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012


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