Ben Bennetts

According to our database1, Ben Bennetts authored at least 23 papers between 1971 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2007
Electronics Design-for-Test: Past, Present and Future.
Proceedings of the 12th European Test Symposium, 2007

2006
IEEE P1687: Toward Standardized Access of Embedded Instrumentation.
Proceedings of the 2006 IEEE International Test Conference, 2006

New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).
Proceedings of the 11th European Test Symposium, 2006

2005
IJTAG (internal JTAG): a step toward a DFT standard.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6.
Proceedings of the 2004 Design, 2004

2003
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.
IEEE Des. Test Comput., 2003

Guest Editors' Introduction: Board Test.
IEEE Des. Test Comput., 2003

1999
Boundary Scan: The Internet of Test.
IEEE Des. Test Comput., 1999

Guest Editors' Introduction: Test and the Product Life Cycle.
IEEE Des. Test Comput., 1999

1996
Built-In Self-Test: Assuring System Integrity.
Computer, 1996

1995
Guest Editor's Introduction.
IEEE Des. Test Comput., 1995

1993
Essential reading for the basics and implementation of boundary scan: Parker, K PThe boundary-scan handbook Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9270 1, £48.00/Dfl. 160.00, pp 282.
Microprocess. Microsystems, 1993

1992
Macro Testability: The Results of Production Device Applications.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Progress in DFT: A Personal View.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status.
J. Electron. Test., 1991

Scan Technology at Work.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

1990
Test Technology in Europe.
IEEE Des. Test Comput., 1990

1986
Digital test text caters for academia and researchers: Hideo Fujiwara 'Logic testing and design for testability' MIT Press, Cambridge, MA, USA (1985) £34.95 pp x + 284.
Microprocess. Microsystems, 1986

1979
Fault tolerance and digital systems.
Microprocess. Microsystems, 1979

1976
Recent Developments in the Theory and Practice of Testable Logic Design.
Computer, 1976

1972
A realistic approach to detection test generation for combinatorial logic circuits.
Comput. J., 1972

1971
An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks.
IEEE Trans. Computers, 1971

Fault Diagnosis of Digital Systems - A Review.
Comput. J., 1971


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