Belliappa Kuttanna
According to our database1,
Belliappa Kuttanna
authored at least 12 papers
between 1993 and 2021.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2021
REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute.
CoRR, 2020
2019
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2015
IEEE Micro, 2015
2011
Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture.
Proceedings of the 8th Conference on Computing Frontiers, 2011
2009
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
2008
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
1997
Proceedings of the Proceedings IEEE COMPCON 97, 1997
Proceedings of the Proceedings IEEE COMPCON 97, 1997
1995
Proceedings of the COMPCON '95: Technologies for the Information Superhighway, 1995
1993
Proceedings of the Sixth International Conference on VLSI Design, 1993