Behzad Salami
Orcid: 0000-0003-4043-5044Affiliations:
- Barcelona Supercomputing Center, Spain
According to our database1,
Behzad Salami
authored at least 38 papers
between 2011 and 2024.
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Bibliography
2024
Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM Performance in FPGA.
Proceedings of the 36th IEEE International Symposium on Computer Architecture and High Performance Computing, 2024
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024
Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024
2023
ACM Trans. Archit. Code Optim., March, 2023
Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips.
CoRR, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Micro, 2022
CoRR, 2022
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators.
CoRR, 2022
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
On the Impact of Device-Level Techniques on Energy-Efficiency of Neural Network Accelerators.
CoRR, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
CoRR, 2020
Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation.
CoRR, 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
CoRR, 2019
Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
2018
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Microprocess. Microsystems, 2017
2016
Comput. Sci. Eng., 2016
Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique.
Proceedings of the High Performance Computing - Third Latin American Conference, 2016
2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
2011
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011