Behzad Mesgarzadeh

According to our database1, Behzad Mesgarzadeh authored at least 24 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Simultaneous switching noise reduction by resonant clock distribution networks.
Integr., 2014

A self-calibration technique for fast-switching frequency-hopped UWB synthesis.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A quadrature UWB frequency synthesizer with dynamic settling-time calibration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A process variation tolerant DLL-based UWB frequency synthesizer.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A Class-D stage with harmonic suppression and DLL-based phase generation.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A DLL-based injection-locked frequency synthesizer for WiMedia UWB.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Reliability challenges in avionics due to silicon aging.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
A multi-segment clocking scheme to reduce on-chip EMI.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
EMI reduction by resonant clock distribution networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode.
IEEE J. Solid State Circuits, 2009

2008
A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS.
Proceedings of the ESSCIRC 2008, 2008

2007
Jitter Characteristic in Charge Recovery Resonant Clock Distribution.
IEEE J. Solid State Circuits, 2007

2006
A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

First-Harmonic Injection-Locked Ring Oscillators.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

1.56 GHz On-chip Resonant Clocking in 130nm CMOS.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Synchronous latency-insensitive design for multiple clock domain.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A study of injection locking in ring oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A new mesochronous clocking scheme for synchronization in SoC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A CMOS implementation of current-mode min-max circuits and a sample fuzzy application.
Proceedings of the IEEE International Conference on Fuzzy Systems, 2004


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