Behzad Dehlaghi

According to our database, Behzad Dehlaghi authored at least 6 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs.

Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2016

A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication.

Behzad Dehlaghi, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2016

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.

Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS.

Behzad Dehlaghi, Anthony Chan Carusone

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals.

Behzad Dehlaghi, Sebastian Magierowski, Leonid Belostotski

IEEE Trans. Very Large Scale Integr. Syst., 2014