Behnam Sedighi

According to our database1, Behnam Sedighi authored at least 32 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Efficient Analog Circuits for Boolean Satisfiability.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2016
Design of latches and flip-flops using emerging tunneling devices.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Analog Circuit Design Using Tunnel-FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A CNN-inspired mixed signal processor based on tunnel transistors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Power-Efficiency Considerations for Adaptive Long-Haul Optical Transceivers.
JOCN, 2014

Nontraditional Computation Using Beyond-CMOS Tunneling Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Architectural impacts of emerging transistors.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Timing errors in LDPC decoding computations with overscaled supply voltage.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Boolean circuit design using emerging tunneling devices.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Cellular neural networks for image analysis using steep slope devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Modeling steep slope devices: From circuits to architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Micro-watt inductorless gm-boost LNA for biomedical implants.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Low-Power SiGe BiCMOS Transimpedance Amplifier for 25-GBaud Optical Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Energy Efficiency of Optical Transceivers in Fiber Access Networks [Invited].
JOCN, 2012

Design of the internal DAC in SAR ADCs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Design of hybrid resistive-capacitive DAC for SAR A/D converters.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A Comparative Analysis of Peaking Methods for Output Stages of Broadband Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009
Linearity analysis in pipeline A/D converters.
Int. J. Circuit Theory Appl., 2009

2007
Variable gain current mirror for high-speed applications.
IEICE Electron. Express, 2007

Wide-range single-ended CMOS track-and-hold circuit.
IEICE Electron. Express, 2007

An 8-bit Switched-Resistor Pipeline ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New High-Speed Class-AB Current-Mode Circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Non-Linear Neural D/A Converter for Direct Digital Frequency Synthesizers.
Proceedings of the International Joint Conference on Neural Networks, 2006

A New Class AB Current-Mode Circuit for Low-Voltage Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

INL Prediction Method in Pipeline ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A new architecture for analog sampled-data neural filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 1.5V 150MS/s current-mode sample-and-hold circuit.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A 1.5V 60MS/s sampled-data filter in 0.18μm CMOS.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005


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