Behnam Khaleghi

Orcid: 0000-0002-3655-0501

According to our database1, Behnam Khaleghi authored at least 56 papers between 2014 and 2024.

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Bibliography

2024
FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing.
CoRR, 2024

HDReason: Algorithm-Hardware Codesign for Hyperdimensional Knowledge Graph Reasoning.
CoRR, 2024

High-Performance Reconfigurable Accelerator for Knowledge Graph Reasoning.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

HD-Bind: Encoding of Molecular Structure with Low Precision, Hyperdimensional Binary Representations.
CoRR, 2023

HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Hierarchical, Distributed and Brain-Inspired Learning for Internet of Things Systems.
Proceedings of the 43rd IEEE International Conference on Distributed Computing Systems, 2023

2022
HyDREA: Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System.
ACM Trans. Embed. Comput. Syst., November, 2022

Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy.
ACM Trans. Embed. Comput. Syst., 2022

OpenHD: A GPU-Powered Framework for Hyperdimensional Computing.
IEEE Trans. Computers, 2022

Streaming Encoding Algorithms for Scalable Hyperdimensional Computing.
CoRR, 2022

TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature Extraction.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

SALIENT: Ultra-Fast FPGA-based Short Read Alignment.
Proceedings of the International Conference on Field-Programmable Technology, 2022

HyperSpike: HyperDimensional Computing for More Efficient and Robust Spiking Neural Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PatterNet: explore and exploit filter patterns for efficient deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

GENERIC: highly efficient learning engine on edge using hyperdimensional computing.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

FAST: FPGA-based Acceleration of Genomic Sequence Trimming.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Stochastic-HD: Leveraging Stochastic Computing on Hyper-Dimensional Computing.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

HyDREA: Towards More Robust and Efficient Machine Learning Systems with Hyperdimensional Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

TruLook: A Framework for Configurable GPU Approximation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Attention State Classification with In-Ear EEG.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
SHEARer: Highly-Efficient Hyperdimensional Computing by Software-Hardware Enabled Multifold Approximation.
CoRR, 2020

SHEAR<i>er</i>: highly-efficient hyperdimensional computing by software-hardware enabled multifold approximation.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Revisiting FPGA Routing under Varying Operating Conditions.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Prive-HD: Privacy-Preserved Hyperdimensional Computing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Estimating and Mitigating Aging Effects in Routing Network of FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

FPGA Energy Efficiency by Leveraging Thermal Margin.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms.
Proceedings of the International Conference on Computer-Aided Design, 2019

F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Thermal-Aware Design and Flow for FPGA Performance Improvement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era.
Adv. Comput., 2018

Voltage Adaptation Under Temperature Variation.
Proceedings of the 15th International Conference on Synthesis, 2018

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era.
IEEE Trans. Computers, 2017

A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing temperature guardbands.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Towards Aging-Induced Approximations.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst., 2016

TooT: an efficient and scalable power-gating method for NoC routers.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Stress-aware routing to mitigate aging effects in SRAM-based FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Reliability-aware design to suppress aging.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2015

FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic.
IEEE Embed. Syst. Lett., 2015

An efficient reconfigurable architecture by characterizing most frequent logic functions.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Towards dark silicon era in FPGAs using complementary hard logic design.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A power-efficient reconfigurable architecture using PCM configuration technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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